[PATCH] D89510: AMDGPU: Fix not always reserving VGPRs used for SGPR spilling
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 15 16:13:30 PDT 2020
arsenm created this revision.
arsenm added reviewers: saiislam, rampitec.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
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arsenm requested review of this revision.
Herald added a subscriber: wdng.
The VGPRs used for SGPR spills need to be reserved, even if we aren't
speculatively reserving one.
This was broken by 117e5609e98b43f925c678b72f816ad3a1c3eee7 <https://reviews.llvm.org/rG117e5609e98b43f925c678b72f816ad3a1c3eee7>.
https://reviews.llvm.org/D89510
Files:
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
Index: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -332,9 +332,8 @@
for (MCPhysReg Reg : MFI->getVGPRSpillAGPRs())
reserveRegisterTuples(Reserved, Reg);
- if (MFI->VGPRReservedForSGPRSpill)
- for (auto SSpill : MFI->getSGPRSpillVGPRs())
- reserveRegisterTuples(Reserved, SSpill.VGPR);
+ for (auto SSpill : MFI->getSGPRSpillVGPRs())
+ reserveRegisterTuples(Reserved, SSpill.VGPR);
return Reserved;
}
Index: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -352,6 +352,8 @@
Register LaneVGPR = TRI->findUnusedRegister(
MF.getRegInfo(), &AMDGPU::VGPR_32RegClass, MF, true);
+ if (LaneVGPR == Register())
+ return false;
SpillVGPRs.push_back(SGPRSpillVGPRCSR(LaneVGPR, None));
FuncInfo->VGPRReservedForSGPRSpill = LaneVGPR;
return true;
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