[llvm] a91dd3d - [VE] Add VGT/VSC/PFCHV instructions
Kazushi Marukawa via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 15 14:28:32 PDT 2020
Author: Kazushi (Jam) Marukawa
Date: 2020-10-16T06:28:22+09:00
New Revision: a91dd3d37d3f10831e544c5a797b3837b7e5744a
URL: https://github.com/llvm/llvm-project/commit/a91dd3d37d3f10831e544c5a797b3837b7e5744a
DIFF: https://github.com/llvm/llvm-project/commit/a91dd3d37d3f10831e544c5a797b3837b7e5744a.diff
LOG: [VE] Add VGT/VSC/PFCHV instructions
Add VGT/VSC/PFCHV vector instructions and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D89471
Added:
llvm/test/MC/VE/PFCHV.s
llvm/test/MC/VE/VGT.s
llvm/test/MC/VE/VSC.s
Modified:
llvm/lib/Target/VE/VEInstrVec.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/VE/VEInstrVec.td b/llvm/lib/Target/VE/VEInstrVec.td
index c752e5c16176..3ed3541a7172 100644
--- a/llvm/lib/Target/VE/VEInstrVec.td
+++ b/llvm/lib/Target/VE/VEInstrVec.td
@@ -144,3 +144,142 @@ defm VSTU2D : VSTm<"vstu2d", 0xd2, V64>;
// Section 8.9.12 - VSTL2D (Vector Store Lower 2D)
defm VSTL2D : VSTm<"vstl2d", 0xd3, V64>;
+
+// Multiclass for VGT instructions
+let mayLoad = 1, hasSideEffects = 0, Uses = [VL] in
+multiclass VGTbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
+ dag dag_in, string disEnc = ""> {
+ let DisableEncoding = disEnc in
+ def "" : RVM<opc, (outs RC:$vx), dag_in,
+ !strconcat(opcStr, " $vx, ", argStr)>;
+ let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base",
+ isCodeGenOnly = 1 in
+ def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
+ !strconcat(opcStr, " $vx, ", argStr)>;
+}
+multiclass VGTlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
+ dag dag_in> {
+ defm "" : VGTbm<opcStr, argStr, opc, RC, dag_in>;
+ let isCodeGenOnly = 1, VE_VLInUse = 1 in {
+ defm l : VGTbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
+ "$vl,">;
+ defm L : VGTbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
+ "$vl,">;
+ }
+}
+multiclass VGTmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
+ dag dag_in> {
+ defm "" : VGTlm<opcStr, argStr, opc, RC, dag_in>;
+ let m = ?, VE_VLWithMask = 1 in
+ defm m : VGTlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins VM:$m))>;
+}
+let VE_VLIndex = 4 in
+multiclass VGTlhm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
+ dag dag_in> {
+ defm rr : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
+ !con(dag_in, (ins I64:$sy, I64:$sz))>;
+ let cy = 0 in
+ defm ir : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
+ !con(dag_in, (ins simm7:$sy, I64:$sz))>;
+ let cz = 0 in
+ defm rz : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
+ !con(dag_in, (ins I64:$sy, zero:$sz))>;
+ let cy = 0, cz = 0 in
+ defm iz : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
+ !con(dag_in, (ins simm7:$sy, zero:$sz))>;
+}
+multiclass VGTtgm<string opcStr, bits<8>opc, RegisterClass RC> {
+ let vy = ? in defm v : VGTlhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>;
+ let cs = 1, sw = ? in defm s : VGTlhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>;
+}
+multiclass VGTm<string opcStr, bits<8>opc, RegisterClass RC> {
+ let vc = 1 in defm "" : VGTtgm<opcStr, opc, RC>;
+ let vc = 0 in defm NC : VGTtgm<opcStr#".nc", opc, RC>;
+}
+
+// Section 8.9.13 - VGT (Vector Gather)
+defm VGT : VGTm<"vgt", 0xa1, V64>;
+
+// Section 8.9.14 - VGTU (Vector Gather Upper)
+defm VGTU : VGTm<"vgtu", 0xa2, V64>;
+
+// Section 8.9.15 - VGTL (Vector Gather Lower)
+defm VGTLSX : VGTm<"vgtl.sx", 0xa3, V64>;
+let cx = 1 in defm VGTLZX : VGTm<"vgtl.zx", 0xa3, V64>;
+def : MnemonicAlias<"vgtl", "vgtl.zx">;
+def : MnemonicAlias<"vgtl.nc", "vgtl.zx.nc">;
+
+// Multiclass for VSC instructions
+let mayStore = 1, hasSideEffects = 0, Uses = [VL] in
+multiclass VSCbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
+ def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>;
+ let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
+ def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)),
+ !strconcat(opcStr, argStr)>;
+ def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)),
+ !strconcat(opcStr, argStr)>;
+ }
+}
+multiclass VSCmm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
+ defm "" : VSCbm<opcStr, argStr, opc, dag_in>;
+ let m = ?, VE_VLWithMask = 1 in
+ defm m : VSCbm<opcStr, argStr#", $m", opc, !con(dag_in, (ins VM:$m))>;
+}
+let VE_VLIndex = 4 in
+multiclass VSClhm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
+ dag dag_in> {
+ defm rrv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
+ !con(dag_in, (ins I64:$sy, I64:$sz, RC:$vx))>;
+ let cy = 0 in
+ defm irv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
+ !con(dag_in, (ins simm7:$sy, I64:$sz, RC:$vx))>;
+ let cz = 0 in
+ defm rzv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
+ !con(dag_in, (ins I64:$sy, zero:$sz, RC:$vx))>;
+ let cy = 0, cz = 0 in
+ defm izv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
+ !con(dag_in, (ins simm7:$sy, zero:$sz, RC:$vx))>;
+}
+multiclass VSCtgm<string opcStr, bits<8>opc, RegisterClass RC> {
+ let vy = ? in defm v : VSClhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>;
+ let cs = 1, sw = ? in defm s : VSClhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>;
+}
+multiclass VSCm<string opcStr, bits<8>opc, RegisterClass RC> {
+ let vc = 1, cx = 0 in defm "" : VSCtgm<opcStr, opc, RC>;
+ let vc = 0, cx = 0 in defm NC : VSCtgm<opcStr#".nc", opc, RC>;
+ let vc = 1, cx = 1 in defm OT : VSCtgm<opcStr#".ot", opc, RC>;
+ let vc = 0, cx = 1 in defm NCOT : VSCtgm<opcStr#".nc.ot", opc, RC>;
+}
+
+// Section 8.9.16 - VSC (Vector Scatter)
+defm VSC : VSCm<"vsc", 0xb1, V64>;
+
+// Section 8.9.17 - VSCU (Vector Scatter Upper)
+defm VSCU : VSCm<"vscu", 0xb2, V64>;
+
+// Section 8.9.18 - VSCL (Vector Scatter Lower)
+defm VSCL : VSCm<"vscl", 0xb3, V64>;
+
+// Section 8.9.19 - PFCHV (Prefetch Vector)
+let Uses = [VL] in
+multiclass PFCHVbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
+ def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>;
+ let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
+ def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)),
+ !strconcat(opcStr, argStr)>;
+ def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)),
+ !strconcat(opcStr, argStr)>;
+ }
+}
+let VE_VLIndex = 2 in
+multiclass PFCHVm<string opcStr, bits<8>opc> {
+ defm rr : PFCHVbm<opcStr, " $sy, $sz", opc, (ins I64:$sy, I64:$sz)>;
+ let cy = 0 in
+ defm ir : PFCHVbm<opcStr, " $sy, $sz", opc, (ins simm7:$sy, I64:$sz)>;
+ let cz = 0 in
+ defm rz : PFCHVbm<opcStr, " $sy, $sz", opc, (ins I64:$sy, zero:$sz)>;
+ let cy = 0, cz = 0 in
+ defm iz : PFCHVbm<opcStr, " $sy, $sz", opc, (ins simm7:$sy, zero:$sz)>;
+}
+let vc = 1, vx = 0 in defm PFCHV : PFCHVm<"pfchv", 0x80>;
+let vc = 0, vx = 0 in defm PFCHVNC : PFCHVm<"pfchv.nc", 0x80>;
diff --git a/llvm/test/MC/VE/PFCHV.s b/llvm/test/MC/VE/PFCHV.s
new file mode 100644
index 000000000000..ad5a2b90a290
--- /dev/null
+++ b/llvm/test/MC/VE/PFCHV.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: pfchv 32, 0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x20,0x40,0x80]
+pfchv 32, 0
+
+# CHECK-INST: pfchv.nc %s11, 0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8b,0x00,0x80]
+pfchv.nc %s11, 0
+
+# CHECK-INST: pfchv -4, %s13
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8d,0x7c,0x40,0x80]
+pfchv -4, %s13
+
+# CHECK-INST: pfchv.nc %s10, %s60
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0xbc,0x8a,0x00,0x80]
+pfchv.nc %s10, %s60
diff --git a/llvm/test/MC/VE/VGT.s b/llvm/test/MC/VE/VGT.s
new file mode 100644
index 000000000000..963007ddbf38
--- /dev/null
+++ b/llvm/test/MC/VE/VGT.s
@@ -0,0 +1,52 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: vgt %v11, %v13, 23, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x0d,0x0b,0x8c,0x17,0x40,0xa1]
+vgt %v11, %v13, 23, %s12
+
+# CHECK-INST: vgt.nc %vix, %s12, 63, 0
+# CHECK-ENCODING: encoding: [0x0c,0x00,0x00,0xff,0x00,0x3f,0x20,0xa1]
+vgt.nc %vix, %s12, 63, 0
+
+# CHECK-INST: vgt %v63, %vix, -64, %s63
+# CHECK-ENCODING: encoding: [0x00,0x00,0xff,0x3f,0xbf,0x40,0x40,0xa1]
+vgt %v63, %vix, -64, %s63
+
+# CHECK-INST: vgt.nc %v12, %v63, %s12, 0, %vm3
+# CHECK-ENCODING: encoding: [0x00,0x00,0x3f,0x0c,0x00,0x8c,0x03,0xa1]
+vgt.nc %v12, %v63, %s12, 0, %vm3
+
+# CHECK-INST: vgtu %v11, %v13, 23, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x0d,0x0b,0x8c,0x17,0x40,0xa2]
+vgtu %v11, %v13, 23, %s12
+
+# CHECK-INST: vgtu.nc %vix, %s12, 63, 0
+# CHECK-ENCODING: encoding: [0x0c,0x00,0x00,0xff,0x00,0x3f,0x20,0xa2]
+vgtu.nc %vix, %s12, 63, 0
+
+# CHECK-INST: vgtu %v63, %vix, -64, %s63
+# CHECK-ENCODING: encoding: [0x00,0x00,0xff,0x3f,0xbf,0x40,0x40,0xa2]
+vgtu %v63, %vix, -64, %s63
+
+# CHECK-INST: vgtu.nc %v12, %v63, %s12, 0, %vm3
+# CHECK-ENCODING: encoding: [0x00,0x00,0x3f,0x0c,0x00,0x8c,0x03,0xa2]
+vgtu.nc %v12, %v63, %s12, 0, %vm3
+
+# CHECK-INST: vgtl.sx %v11, %v13, 23, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x0d,0x0b,0x8c,0x17,0x40,0xa3]
+vgtl.sx %v11, %v13, 23, %s12
+
+# CHECK-INST: vgtl.zx.nc %vix, %s12, 63, 0
+# CHECK-ENCODING: encoding: [0x0c,0x00,0x00,0xff,0x00,0x3f,0xa0,0xa3]
+vgtl.nc %vix, %s12, 63, 0
+
+# CHECK-INST: vgtl.zx %v63, %vix, -64, %s63
+# CHECK-ENCODING: encoding: [0x00,0x00,0xff,0x3f,0xbf,0x40,0xc0,0xa3]
+vgtl.zx %v63, %vix, -64, %s63
+
+# CHECK-INST: vgtl.sx.nc %v12, %v63, %s12, 0, %vm3
+# CHECK-ENCODING: encoding: [0x00,0x00,0x3f,0x0c,0x00,0x8c,0x03,0xa3]
+vgtl.sx.nc %v12, %v63, %s12, 0, %vm3
diff --git a/llvm/test/MC/VE/VSC.s b/llvm/test/MC/VE/VSC.s
new file mode 100644
index 000000000000..69120d7bc1ce
--- /dev/null
+++ b/llvm/test/MC/VE/VSC.s
@@ -0,0 +1,52 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: vsc %v11, %v13, 23, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x0d,0x0b,0x8c,0x17,0x40,0xb1]
+vsc %v11, %v13, 23, %s12
+
+# CHECK-INST: vsc.nc %vix, %s12, 63, 0
+# CHECK-ENCODING: encoding: [0x0c,0x00,0x00,0xff,0x00,0x3f,0x20,0xb1]
+vsc.nc %vix, %s12, 63, 0
+
+# CHECK-INST: vsc.ot %v63, %vix, -64, %s63
+# CHECK-ENCODING: encoding: [0x00,0x00,0xff,0x3f,0xbf,0x40,0xc0,0xb1]
+vsc.ot %v63, %vix, -64, %s63
+
+# CHECK-INST: vsc.nc.ot %v12, %v63, %s12, 0, %vm3
+# CHECK-ENCODING: encoding: [0x00,0x00,0x3f,0x0c,0x00,0x8c,0x83,0xb1]
+vsc.nc.ot %v12, %v63, %s12, 0, %vm3
+
+# CHECK-INST: vscu %v11, %v13, 23, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x0d,0x0b,0x8c,0x17,0x40,0xb2]
+vscu %v11, %v13, 23, %s12
+
+# CHECK-INST: vscu.nc %vix, %s12, 63, 0
+# CHECK-ENCODING: encoding: [0x0c,0x00,0x00,0xff,0x00,0x3f,0x20,0xb2]
+vscu.nc %vix, %s12, 63, 0
+
+# CHECK-INST: vscu.ot %v63, %vix, -64, %s63
+# CHECK-ENCODING: encoding: [0x00,0x00,0xff,0x3f,0xbf,0x40,0xc0,0xb2]
+vscu.ot %v63, %vix, -64, %s63
+
+# CHECK-INST: vscu.nc.ot %v12, %v63, %s12, 0, %vm3
+# CHECK-ENCODING: encoding: [0x00,0x00,0x3f,0x0c,0x00,0x8c,0x83,0xb2]
+vscu.nc.ot %v12, %v63, %s12, 0, %vm3
+
+# CHECK-INST: vscl %v11, %v13, 23, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x0d,0x0b,0x8c,0x17,0x40,0xb3]
+vscl %v11, %v13, 23, %s12
+
+# CHECK-INST: vscl.ot %vix, %s12, 63, 0
+# CHECK-ENCODING: encoding: [0x0c,0x00,0x00,0xff,0x00,0x3f,0xe0,0xb3]
+vscl.ot %vix, %s12, 63, 0
+
+# CHECK-INST: vscl.nc %v63, %vix, -64, %s63
+# CHECK-ENCODING: encoding: [0x00,0x00,0xff,0x3f,0xbf,0x40,0x00,0xb3]
+vscl.nc %v63, %vix, -64, %s63
+
+# CHECK-INST: vscl.nc.ot %v12, %v63, %s12, 0, %vm3
+# CHECK-ENCODING: encoding: [0x00,0x00,0x3f,0x0c,0x00,0x8c,0x83,0xb3]
+vscl.nc.ot %v12, %v63, %s12, 0, %vm3
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