[llvm] dfdfcdc - [NFC][LSR] Autogenerate check lines in tests being affected by upcoming patch
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 15 13:15:39 PDT 2020
Author: Roman Lebedev
Date: 2020-10-15T23:15:04+03:00
New Revision: dfdfcdc8d3c99cfe9fdef7c604ecc3b165e79572
URL: https://github.com/llvm/llvm-project/commit/dfdfcdc8d3c99cfe9fdef7c604ecc3b165e79572
DIFF: https://github.com/llvm/llvm-project/commit/dfdfcdc8d3c99cfe9fdef7c604ecc3b165e79572.diff
LOG: [NFC][LSR] Autogenerate check lines in tests being affected by upcoming patch
Added:
Modified:
llvm/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll
llvm/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll b/llvm/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll
index 5f910ce8402d..d851499e25dc 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -loop-reduce -S < %s | FileCheck %s
;
; Test LSR's use of SplitCriticalEdge during phi rewriting.
@@ -7,13 +8,40 @@ target triple = "x86_64-apple-darwin"
; Provide legal integer types.
target datalayout = "n8:16:32:64"
-
; Verify that identical edges are merged. rdar://problem/6453893
-; CHECK-LABEL: @test1(
-; CHECK: bb89:
-; CHECK: phi i8* [ %lsr.iv.next1, %bbA.bb89_crit_edge ], [ %lsr.iv.next1, %bbB.bb89_crit_edge ]{{$}}
define i8* @test1() {
+;
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i64 [[LSR_IV]], 1
+; CHECK-NEXT: [[LSR_IV_NEXT1:%.*]] = inttoptr i64 [[LSR_IV_NEXT]] to i8*
+; CHECK-NEXT: br i1 false, label [[LOOP]], label [[LOOPEXIT:%.*]]
+; CHECK: loopexit:
+; CHECK-NEXT: br i1 false, label [[BBA:%.*]], label [[BBB:%.*]]
+; CHECK: bbA:
+; CHECK-NEXT: switch i32 0, label [[BBA_BB89_CRIT_EDGE:%.*]] [
+; CHECK-NEXT: i32 47, label [[BBA_BB89_CRIT_EDGE]]
+; CHECK-NEXT: i32 58, label [[BBA_BB89_CRIT_EDGE]]
+; CHECK-NEXT: ]
+; CHECK: bbA.bb89_crit_edge:
+; CHECK-NEXT: br label [[BB89:%.*]]
+; CHECK: bbB:
+; CHECK-NEXT: switch i8 0, label [[BBB_BB89_CRIT_EDGE:%.*]] [
+; CHECK-NEXT: i8 47, label [[BBB_BB89_CRIT_EDGE]]
+; CHECK-NEXT: i8 58, label [[BBB_BB89_CRIT_EDGE]]
+; CHECK-NEXT: ]
+; CHECK: bbB.bb89_crit_edge:
+; CHECK-NEXT: br label [[BB89]]
+; CHECK: bb89:
+; CHECK-NEXT: [[TMP75PHI:%.*]] = phi i8* [ [[LSR_IV_NEXT1]], [[BBA_BB89_CRIT_EDGE]] ], [ [[LSR_IV_NEXT1]], [[BBB_BB89_CRIT_EDGE]] ]
+; CHECK-NEXT: br label [[EXIT:%.*]]
+; CHECK: exit:
+; CHECK-NEXT: ret i8* [[TMP75PHI]]
+;
entry:
br label %loop
@@ -28,14 +56,14 @@ loopexit:
bbA:
switch i32 0, label %bb89 [
- i32 47, label %bb89
- i32 58, label %bb89
+ i32 47, label %bb89
+ i32 58, label %bb89
]
bbB:
switch i8 0, label %bb89 [
- i8 47, label %bb89
- i8 58, label %bb89
+ i8 47, label %bb89
+ i8 58, label %bb89
]
bb89:
@@ -47,10 +75,37 @@ exit:
}
; Handle single-predecessor phis: PR13756
-; CHECK-LABEL: @test2(
-; CHECK: bb89:
-; CHECK: phi i8* [ %lsr.iv.next1, %bbA ], [ %lsr.iv.next1, %bbA ], [ %lsr.iv.next1, %bbA ]{{$}}
define i8* @test2() {
+;
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i64 [[LSR_IV]], 1
+; CHECK-NEXT: [[LSR_IV_NEXT1:%.*]] = inttoptr i64 [[LSR_IV_NEXT]] to i8*
+; CHECK-NEXT: br i1 false, label [[LOOP]], label [[LOOPEXIT:%.*]]
+; CHECK: loopexit:
+; CHECK-NEXT: br i1 false, label [[BBA:%.*]], label [[BBB:%.*]]
+; CHECK: bbA:
+; CHECK-NEXT: switch i32 0, label [[BB89:%.*]] [
+; CHECK-NEXT: i32 47, label [[BB89]]
+; CHECK-NEXT: i32 58, label [[BB89]]
+; CHECK-NEXT: ]
+; CHECK: bbB:
+; CHECK-NEXT: switch i8 0, label [[BBB_EXIT_CRIT_EDGE:%.*]] [
+; CHECK-NEXT: i8 47, label [[BBB_EXIT_CRIT_EDGE]]
+; CHECK-NEXT: i8 58, label [[BBB_EXIT_CRIT_EDGE]]
+; CHECK-NEXT: ]
+; CHECK: bbB.exit_crit_edge:
+; CHECK-NEXT: br label [[EXIT:%.*]]
+; CHECK: bb89:
+; CHECK-NEXT: [[TMP75PHI:%.*]] = phi i8* [ [[LSR_IV_NEXT1]], [[BBA]] ], [ [[LSR_IV_NEXT1]], [[BBA]] ], [ [[LSR_IV_NEXT1]], [[BBA]] ]
+; CHECK-NEXT: br label [[EXIT]]
+; CHECK: exit:
+; CHECK-NEXT: [[RESULT:%.*]] = phi i8* [ [[TMP75PHI]], [[BB89]] ], [ [[LSR_IV_NEXT1]], [[BBB_EXIT_CRIT_EDGE]] ]
+; CHECK-NEXT: ret i8* [[RESULT]]
+;
entry:
br label %loop
@@ -65,14 +120,14 @@ loopexit:
bbA:
switch i32 0, label %bb89 [
- i32 47, label %bb89
- i32 58, label %bb89
+ i32 47, label %bb89
+ i32 58, label %bb89
]
bbB:
switch i8 0, label %exit [
- i8 47, label %exit
- i8 58, label %exit
+ i8 47, label %exit
+ i8 58, label %exit
]
bb89:
diff --git a/llvm/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll b/llvm/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll
index 79a0e79b4396..245b38325565 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll
@@ -1,21 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -loop-reduce -S < %s | FileCheck %s
; PR9939
; LSR should properly handle the post-inc offset when folding the
; non-IV operand of an icmp into the IV.
-; CHECK: [[r1:%[a-z0-9\.]+]] = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast
-; CHECK: [[r2:%[a-z0-9\.]+]] = lshr exact i64 [[r1]], 1
-; CHECK: [[r3:%[a-z0-9\.]+]] = bitcast i64 [[r2]] to i64
-; CHECK: for.body.lr.ph:
-; CHECK: [[r4:%[a-z0-9]+]] = shl nuw i64 [[r3]], 1
-; CHECK: br label %for.body
-; CHECK: for.body:
-; CHECK: %lsr.iv2 = phi i64 [ %lsr.iv.next, %for.body ], [ [[r4]], %for.body.lr.ph ]
-; CHECK: %lsr.iv.next = add i64 %lsr.iv2, -2
-; CHECK: %lsr.iv.next3 = inttoptr i64 %lsr.iv.next to i16*
-; CHECK: %cmp27 = icmp eq i16* %lsr.iv.next3, null
-
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
%struct.Vector2 = type { i16*, [64 x i16], i32 }
@@ -23,6 +12,77 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
@.str = private unnamed_addr constant [37 x i8] c"0123456789abcdefghijklmnopqrstuvwxyz\00"
define void @_Z15IntegerToStringjjR7Vector2(i32 %i, i32 %radix, %struct.Vector2* nocapture %result) nounwind noinline {
+; CHECK-LABEL: @_Z15IntegerToStringjjR7Vector2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[BUFFER:%.*]] = alloca [33 x i16], align 16
+; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds [33 x i16], [33 x i16]* [[BUFFER]], i64 0, i64 33
+; CHECK-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i16* [[ADD_PTR]] to i64
+; CHECK-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i16* [[ADD_PTR]] to i64
+; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr [33 x i16], [33 x i16]* [[BUFFER]], i64 0, i64 32
+; CHECK-NEXT: [[SCEVGEP45:%.*]] = bitcast i16* [[SCEVGEP4]] to [33 x i16]*
+; CHECK-NEXT: [[SCEVGEP11:%.*]] = getelementptr [33 x i16], [33 x i16]* [[BUFFER]], i64 1, i64 0
+; CHECK-NEXT: [[SCEVGEP1112:%.*]] = bitcast i16* [[SCEVGEP11]] to [33 x i16]*
+; CHECK-NEXT: br label [[DO_BODY:%.*]]
+; CHECK: do.body:
+; CHECK-NEXT: [[LSR_IV15:%.*]] = phi i64 [ [[LSR_IV_NEXT16:%.*]], [[DO_BODY]] ], [ -1, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[LSR_IV13:%.*]] = phi [33 x i16]* [ [[TMP2:%.*]], [[DO_BODY]] ], [ [[SCEVGEP1112]], [[ENTRY]] ]
+; CHECK-NEXT: [[LSR_IV6:%.*]] = phi [33 x i16]* [ [[TMP1:%.*]], [[DO_BODY]] ], [ [[SCEVGEP45]], [[ENTRY]] ]
+; CHECK-NEXT: [[I_ADDR_0:%.*]] = phi i32 [ [[DIV:%.*]], [[DO_BODY]] ], [ [[I:%.*]], [[ENTRY]] ]
+; CHECK-NEXT: [[LSR_IV617:%.*]] = bitcast [33 x i16]* [[LSR_IV6]] to i16*
+; CHECK-NEXT: [[REM:%.*]] = urem i32 [[I_ADDR_0]], 10
+; CHECK-NEXT: [[DIV]] = udiv i32 [[I_ADDR_0]], 10
+; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[REM]] to i64
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [37 x i8], [37 x i8]* @.str, i64 0, i64 [[IDXPROM]]
+; CHECK-NEXT: [[TMP5:%.*]] = load i8, i8* [[ARRAYIDX]], align 1
+; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP5]] to i16
+; CHECK-NEXT: store i16 [[CONV]], i16* [[LSR_IV617]], align 2
+; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt i32 [[I_ADDR_0]], 9
+; CHECK-NEXT: [[SCEVGEP7:%.*]] = getelementptr [33 x i16], [33 x i16]* [[LSR_IV6]], i64 0, i64 -1
+; CHECK-NEXT: [[TMP1]] = bitcast i16* [[SCEVGEP7]] to [33 x i16]*
+; CHECK-NEXT: [[SCEVGEP14:%.*]] = getelementptr [33 x i16], [33 x i16]* [[LSR_IV13]], i64 0, i64 -1
+; CHECK-NEXT: [[TMP2]] = bitcast i16* [[SCEVGEP14]] to [33 x i16]*
+; CHECK-NEXT: [[LSR_IV_NEXT16]] = add i64 [[LSR_IV15]], 1
+; CHECK-NEXT: br i1 [[TMP0]], label [[DO_BODY]], label [[DO_END:%.*]]
+; CHECK: do.end:
+; CHECK-NEXT: [[XAP_0:%.*]] = inttoptr i64 [[LSR_IV_NEXT16]] to i1*
+; CHECK-NEXT: [[CAP_0:%.*]] = ptrtoint i1* [[XAP_0]] to i64
+; CHECK-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]
+; CHECK-NEXT: [[SUB_PTR_DIV39:%.*]] = lshr exact i64 [[SUB_PTR_SUB]], 1
+; CHECK-NEXT: [[CONV11:%.*]] = trunc i64 [[SUB_PTR_DIV39]] to i32
+; CHECK-NEXT: [[MLENGTH:%.*]] = getelementptr inbounds [[STRUCT_VECTOR2:%.*]], %struct.Vector2* [[RESULT:%.*]], i64 0, i32 2
+; CHECK-NEXT: [[IDX_EXT21:%.*]] = bitcast i64 [[SUB_PTR_DIV39]] to i64
+; CHECK-NEXT: [[CMP2740:%.*]] = icmp eq i64 [[IDX_EXT21]], 0
+; CHECK-NEXT: br i1 [[CMP2740]], label [[FOR_END:%.*]], label [[FOR_BODY_LR_PH:%.*]]
+; CHECK: for.body.lr.ph:
+; CHECK-NEXT: [[TMP16:%.*]] = load i32, i32* [[MLENGTH]], align 4
+; CHECK-NEXT: [[MBEGIN:%.*]] = getelementptr inbounds [[STRUCT_VECTOR2]], %struct.Vector2* [[RESULT]], i64 0, i32 0
+; CHECK-NEXT: [[TMP14:%.*]] = load i16*, i16** [[MBEGIN]], align 8
+; CHECK-NEXT: [[TMP48:%.*]] = zext i32 [[TMP16]] to i64
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i16, i16* [[TMP14]], i64 [[TMP48]]
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[IDX_EXT21]], 1
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[LSR_IV8:%.*]] = phi [33 x i16]* [ [[TMP4:%.*]], [[FOR_BODY]] ], [ [[TMP2]], [[FOR_BODY_LR_PH]] ]
+; CHECK-NEXT: [[LSR_IV2:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[FOR_BODY]] ], [ [[TMP3]], [[FOR_BODY_LR_PH]] ]
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i16* [ [[SCEVGEP1:%.*]], [[FOR_BODY]] ], [ [[SCEVGEP]], [[FOR_BODY_LR_PH]] ]
+; CHECK-NEXT: [[LSR_IV810:%.*]] = bitcast [33 x i16]* [[LSR_IV8]] to i16*
+; CHECK-NEXT: [[TMP29:%.*]] = load i16, i16* [[LSR_IV810]], align 2
+; CHECK-NEXT: store i16 [[TMP29]], i16* [[LSR_IV]], align 2
+; CHECK-NEXT: [[SCEVGEP1]] = getelementptr i16, i16* [[LSR_IV]], i64 1
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV2]], -2
+; CHECK-NEXT: [[LSR_IV_NEXT3:%.*]] = inttoptr i64 [[LSR_IV_NEXT]] to i16*
+; CHECK-NEXT: [[SCEVGEP9:%.*]] = getelementptr [33 x i16], [33 x i16]* [[LSR_IV8]], i64 0, i64 1
+; CHECK-NEXT: [[TMP4]] = bitcast i16* [[SCEVGEP9]] to [33 x i16]*
+; CHECK-NEXT: [[CMP27:%.*]] = icmp eq i16* [[LSR_IV_NEXT3]], null
+; CHECK-NEXT: br i1 [[CMP27]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY]]
+; CHECK: for.end.loopexit:
+; CHECK-NEXT: br label [[FOR_END]]
+; CHECK: for.end:
+; CHECK-NEXT: [[TMP38:%.*]] = load i32, i32* [[MLENGTH]], align 4
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP38]], [[CONV11]]
+; CHECK-NEXT: store i32 [[ADD]], i32* [[MLENGTH]], align 4
+; CHECK-NEXT: ret void
+;
entry:
%buffer = alloca [33 x i16], align 16
%add.ptr = getelementptr inbounds [33 x i16], [33 x i16]* %buffer, i64 0, i64 33
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