[PATCH] D89466: AMDGPU: Implement getNoPreservedMask

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: rampitec.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
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We don't support funclets for exception handling and I hit this when
manually reducing MIR.


https://reviews.llvm.org/D89466

Files:
  llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/test/CodeGen/AMDGPU/return-with-successors.mir


Index: llvm/test/CodeGen/AMDGPU/return-with-successors.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/return-with-successors.mir
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=liveintervals -o - %s | FileCheck %s
+# Test that getNoPreservedMask is implemented, which is called when
+# return blocks have successors.
+
+---
+name: endpgm_with_successors
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: endpgm_with_successors
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   S_ENDPGM 0
+  ; CHECK: bb.1:
+  ; CHECK:   S_NOP 0
+  bb.0:
+    successors: %bb.1
+    S_ENDPGM 0
+
+  bb.1:
+    S_NOP 0
+
+...
+
+---
+name: setpc_with_successors
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: setpc_with_successors
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: $sgpr30_sgpr31
+  ; CHECK:   S_SETPC_B64 $sgpr30_sgpr31
+  ; CHECK: bb.1:
+  ; CHECK:   S_NOP 0
+  bb.0:
+    liveins: $sgpr30_sgpr31
+    successors: %bb.1
+    S_SETPC_B64 $sgpr30_sgpr31
+
+  bb.1:
+    S_NOP 0
+
+...
Index: llvm/lib/Target/AMDGPU/SIRegisterInfo.h
===================================================================
--- llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -68,6 +68,7 @@
   const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID) const override;
+  const uint32_t *getNoPreservedMask() const override;
 
   // Stack access is very expensive. CSRs are also the high registers, and we
   // want to minimize the number of used registers.
Index: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -151,6 +151,10 @@
   }
 }
 
+const uint32_t *SIRegisterInfo::getNoPreservedMask() const {
+  return CSR_AMDGPU_NoRegs_RegMask;
+}
+
 Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const SIFrameLowering *TFI =
       MF.getSubtarget<GCNSubtarget>().getFrameLowering();
Index: llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
+++ llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
@@ -125,6 +125,8 @@
   (add CSR_AMDGPU_VGPRs, CSR_AMDGPU_SGPRs_32_105)
 >;
 
+def CSR_AMDGPU_NoRegs : CalleeSavedRegs<(add)>;
+
 // Calling convention for leaf functions
 def CC_AMDGPU_Func : CallingConv<[
   CCIfByVal<CCPassByVal<4, 4>>,


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