[PATCH] D89415: [AArch64][GlobalISel] Introduce a new post-isel optimization pass

[Jessica Paquette via Phabricator via llvm-commits]

paquette added inline comments.


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp:89
+  bool NZCVIsLive = true;
+  for (auto II = MBB.rbegin(); II != MBB.rend(); ++II) {
+    // If this instruction uses NZCV, then NZCV is live.
----------------
Maybe a little nicer?

```
for (auto &MI : instructionsWithoutDebug(MBB.rbegin(), MBB.rend())
```


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp:91
+    // If this instruction uses NZCV, then NZCV is live.
+    if (II->readsRegister(AArch64::NZCV)) {
+      NZCVIsLive = true;
----------------
Maybe a sledgehammer, but would it make sense to use LiveRegUnits here?

e.g. something like this would probably work?

```
LiveRegUnits LRU(...);
LRU.addLiveOuts(MBB);
bool NZCVDead = LRU.available(AArch64::NZCV);
for (...) {
   LRU.stepBackward(*II);

   // Did this instruction define NZCV?
   bool NZCVDeadAtCurrInstr = LRU.available(AArch64::NZCV);
   if (NZCVDead && !NZCVDeadAtCurrInstr) {
      // If we have a def and NZCV is dead...
   }

   NZCVDead = NZCVDeadAtCurrInstr;
}
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89415/new/

https://reviews.llvm.org/D89415