[llvm] 670cd3c - [Hexagon] Generate better splat code on v62+
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 14 10:55:53 PDT 2020
Author: Krzysztof Parzyszek
Date: 2020-10-14T12:55:20-05:00
New Revision: 670cd3c6e324a1aa012fc478f2f8cb92dab4a87c
URL: https://github.com/llvm/llvm-project/commit/670cd3c6e324a1aa012fc478f2f8cb92dab4a87c
DIFF: https://github.com/llvm/llvm-project/commit/670cd3c6e324a1aa012fc478f2f8cb92dab4a87c.diff
LOG: [Hexagon] Generate better splat code on v62+
Added:
llvm/test/CodeGen/Hexagon/autohvx/splat.ll
Modified:
llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
index b60326ad8fbf..5a5f3e5be07d 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
@@ -199,32 +199,61 @@ let Predicates = [UseHVX] in {
(V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
}
-def Vsplatib: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 (SplatB $V)))>;
-def Vsplatih: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 (SplatH $V)))>;
-def Vsplatiw: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 $V))>;
-
-def Vsplatrb: OutPatFrag<(ops node:$Rs), (V6_lvsplatw (S2_vsplatrb $Rs))>;
-def Vsplatrh: OutPatFrag<(ops node:$Rs),
- (V6_lvsplatw (A2_combine_ll $Rs, $Rs))>;
-def Vsplatrw: OutPatFrag<(ops node:$Rs), (V6_lvsplatw $Rs)>;
+// Splats for HvxV60
+def V60splatib: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 (SplatB $V)))>;
+def V60splatih: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 (SplatH $V)))>;
+def V60splatiw: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 $V))>;
+def V60splatrb: OutPatFrag<(ops node:$Rs), (V6_lvsplatw (S2_vsplatrb $Rs))>;
+def V60splatrh: OutPatFrag<(ops node:$Rs),
+ (V6_lvsplatw (A2_combine_ll $Rs, $Rs))>;
+def V60splatrw: OutPatFrag<(ops node:$Rs), (V6_lvsplatw $Rs)>;
+
+// Splats for HvxV62+
+def V62splatib: OutPatFrag<(ops node:$V), (V6_lvsplatb (ToI32 $V))>;
+def V62splatih: OutPatFrag<(ops node:$V), (V6_lvsplath (ToI32 $V))>;
+def V62splatiw: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 $V))>;
+def V62splatrb: OutPatFrag<(ops node:$Rs), (V6_lvsplatb $Rs)>;
+def V62splatrh: OutPatFrag<(ops node:$Rs), (V6_lvsplath $Rs)>;
+def V62splatrw: OutPatFrag<(ops node:$Rs), (V6_lvsplatw $Rs)>;
def Rep: OutPatFrag<(ops node:$N), (Combinev $N, $N)>;
-let Predicates = [UseHVX] in {
+let Predicates = [UseHVX,UseHVXV60] in {
let AddedComplexity = 10 in {
- def: Pat<(VecI8 (splat_vector u8_0ImmPred:$V)), (Vsplatib $V)>;
- def: Pat<(VecI16 (splat_vector u16_0ImmPred:$V)), (Vsplatih $V)>;
- def: Pat<(VecI32 (splat_vector anyimm:$V)), (Vsplatiw $V)>;
- def: Pat<(VecPI8 (splat_vector u8_0ImmPred:$V)), (Rep (Vsplatib $V))>;
- def: Pat<(VecPI16 (splat_vector u16_0ImmPred:$V)), (Rep (Vsplatih $V))>;
- def: Pat<(VecPI32 (splat_vector anyimm:$V)), (Rep (Vsplatiw $V))>;
+ def: Pat<(VecI8 (splat_vector u8_0ImmPred:$V)), (V60splatib $V)>;
+ def: Pat<(VecI16 (splat_vector u16_0ImmPred:$V)), (V60splatih $V)>;
+ def: Pat<(VecI32 (splat_vector anyimm:$V)), (V60splatiw $V)>;
+ def: Pat<(VecPI8 (splat_vector u8_0ImmPred:$V)), (Rep (V60splatib $V))>;
+ def: Pat<(VecPI16 (splat_vector u16_0ImmPred:$V)), (Rep (V60splatih $V))>;
+ def: Pat<(VecPI32 (splat_vector anyimm:$V)), (Rep (V60splatiw $V))>;
+ }
+ def: Pat<(VecI8 (splat_vector I32:$Rs)), (V60splatrb $Rs)>;
+ def: Pat<(VecI16 (splat_vector I32:$Rs)), (V60splatrh $Rs)>;
+ def: Pat<(VecI32 (splat_vector I32:$Rs)), (V60splatrw $Rs)>;
+ def: Pat<(VecPI8 (splat_vector I32:$Rs)), (Rep (V60splatrb $Rs))>;
+ def: Pat<(VecPI16 (splat_vector I32:$Rs)), (Rep (V60splatrh $Rs))>;
+ def: Pat<(VecPI32 (splat_vector I32:$Rs)), (Rep (V60splatrw $Rs))>;
+}
+let Predicates = [UseHVX,UseHVXV62] in {
+ let AddedComplexity = 30 in {
+ def: Pat<(VecI8 (splat_vector u8_0ImmPred:$V)), (V62splatib imm:$V)>;
+ def: Pat<(VecI16 (splat_vector u16_0ImmPred:$V)), (V62splatih imm:$V)>;
+ def: Pat<(VecI32 (splat_vector anyimm:$V)), (V62splatiw imm:$V)>;
+ def: Pat<(VecPI8 (splat_vector u8_0ImmPred:$V)),
+ (Rep (V62splatib imm:$V))>;
+ def: Pat<(VecPI16 (splat_vector u16_0ImmPred:$V)),
+ (Rep (V62splatih imm:$V))>;
+ def: Pat<(VecPI32 (splat_vector anyimm:$V)),
+ (Rep (V62splatiw imm:$V))>;
+ }
+ let AddedComplexity = 20 in {
+ def: Pat<(VecI8 (splat_vector I32:$Rs)), (V62splatrb $Rs)>;
+ def: Pat<(VecI16 (splat_vector I32:$Rs)), (V62splatrh $Rs)>;
+ def: Pat<(VecI32 (splat_vector I32:$Rs)), (V62splatrw $Rs)>;
+ def: Pat<(VecPI8 (splat_vector I32:$Rs)), (Rep (V62splatrb $Rs))>;
+ def: Pat<(VecPI16 (splat_vector I32:$Rs)), (Rep (V62splatrh $Rs))>;
+ def: Pat<(VecPI32 (splat_vector I32:$Rs)), (Rep (V62splatrw $Rs))>;
}
- def: Pat<(VecI8 (splat_vector I32:$Rs)), (Vsplatrb $Rs)>;
- def: Pat<(VecI16 (splat_vector I32:$Rs)), (Vsplatrh $Rs)>;
- def: Pat<(VecI32 (splat_vector I32:$Rs)), (Vsplatrw $Rs)>;
- def: Pat<(VecPI8 (splat_vector I32:$Rs)), (Rep (Vsplatrb $Rs))>;
- def: Pat<(VecPI16 (splat_vector I32:$Rs)), (Rep (Vsplatrh $Rs))>;
- def: Pat<(VecPI32 (splat_vector I32:$Rs)), (Rep (Vsplatrw $Rs))>;
}
class Vneg1<ValueType VecTy>
@@ -425,10 +454,18 @@ let Predicates = [UseHVX] in {
def: Pat<(VecPI32 (vunpacku HVI8:$Vs)), (VZxth (LoVec (VZxtb $Vs)))>;
def: Pat<(VecPI32 (vunpacku HVI32:$Vs)), (VZxth $Vs)>;
- def: Pat<(VecI16 (bswap HVI16:$Vs)),
- (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x01010101)))>;
- def: Pat<(VecI32 (bswap HVI32:$Vs)),
- (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x03030303)))>;
+ let Predicates = [UseHVX,UseHVXV60] in {
+ def: Pat<(VecI16 (bswap HVI16:$Vs)),
+ (V6_vdelta HvxVR:$Vs, (V60splatib (i32 0x01)))>;
+ def: Pat<(VecI32 (bswap HVI32:$Vs)),
+ (V6_vdelta HvxVR:$Vs, (V60splatib (i32 0x03)))>;
+ }
+ let Predicates = [UseHVX,UseHVXV62], AddedComplexity = 10 in {
+ def: Pat<(VecI16 (bswap HVI16:$Vs)),
+ (V6_vdelta HvxVR:$Vs, (V62splatib (i32 0x01)))>;
+ def: Pat<(VecI32 (bswap HVI32:$Vs)),
+ (V6_vdelta HvxVR:$Vs, (V62splatib (i32 0x03)))>;
+ }
def: Pat<(VecI8 (ctpop HVI8:$Vs)),
(V6_vpackeb (V6_vpopcounth (HiVec (V6_vunpackub HvxVR:$Vs))),
@@ -438,10 +475,17 @@ let Predicates = [UseHVX] in {
(V6_vaddw (LoVec (V6_vzh (V6_vpopcounth HvxVR:$Vs))),
(HiVec (V6_vzh (V6_vpopcounth HvxVR:$Vs))))>;
+ let Predicates = [UseHVX,UseHVXV60] in
def: Pat<(VecI8 (ctlz HVI8:$Vs)),
(V6_vsubb (V6_vpackeb (V6_vcl0h (HiVec (V6_vunpackub HvxVR:$Vs))),
(V6_vcl0h (LoVec (V6_vunpackub HvxVR:$Vs)))),
- (V6_lvsplatw (A2_tfrsi 0x08080808)))>;
+ (V60splatib (i32 0x08)))>;
+ let Predicates = [UseHVX,UseHVXV62], AddedComplexity = 10 in
+ def: Pat<(VecI8 (ctlz HVI8:$Vs)),
+ (V6_vsubb (V6_vpackeb (V6_vcl0h (HiVec (V6_vunpackub HvxVR:$Vs))),
+ (V6_vcl0h (LoVec (V6_vunpackub HvxVR:$Vs)))),
+ (V62splatib (i32 0x08)))>;
+
def: Pat<(VecI16 (ctlz HVI16:$Vs)), (V6_vcl0h HvxVR:$Vs)>;
def: Pat<(VecI32 (ctlz HVI32:$Vs)), (V6_vcl0w HvxVR:$Vs)>;
}
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/splat.ll b/llvm/test/CodeGen/Hexagon/autohvx/splat.ll
new file mode 100644
index 000000000000..c686561f1713
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/autohvx/splat.ll
@@ -0,0 +1,401 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Splat immediate, 8-bit, v60
+define <128 x i8> @f0() #0 {
+; CHECK-LABEL: f0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = ##2139062143
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = vsplat(r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <128 x i8> undef, i8 127, i32 0
+ %v1 = shufflevector <128 x i8> %v0, <128 x i8> undef, <128 x i32> zeroinitializer
+ ret <128 x i8> %v1
+}
+
+; Splat immediate, 16 bit, v60
+define <64 x i16> @f1() #0 {
+; CHECK-LABEL: f1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = ##-1437226411
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = vsplat(r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <64 x i16> undef, i16 43605, i32 0
+ %v1 = shufflevector <64 x i16> %v0, <64 x i16> undef, <64 x i32> zeroinitializer
+ ret <64 x i16> %v1
+}
+
+; Splat immediate, 32 bit, v60
+define <32 x i32> @f2() #0 {
+; CHECK-LABEL: f2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = ##134744072
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = vsplat(r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <32 x i32> undef, i32 134744072, i32 0
+ %v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <32 x i32> zeroinitializer
+ ret <32 x i32> %v1
+}
+
+; Splat immediate, 8-bit, v62+
+define <128 x i8> @f3() #1 {
+; CHECK-LABEL: f3:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = #127
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0.b = vsplat(r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <128 x i8> undef, i8 127, i32 0
+ %v1 = shufflevector <128 x i8> %v0, <128 x i8> undef, <128 x i32> zeroinitializer
+ ret <128 x i8> %v1
+}
+
+; Splat immediate, 16 bit, v62+
+define <64 x i16> @f4() #1 {
+; CHECK-LABEL: f4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = #-21931
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0.h = vsplat(r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <64 x i16> undef, i16 43605, i32 0
+ %v1 = shufflevector <64 x i16> %v0, <64 x i16> undef, <64 x i32> zeroinitializer
+ ret <64 x i16> %v1
+}
+
+; Splat immediate, 32 bit, v62+
+define <32 x i32> @f5() #1 {
+; CHECK-LABEL: f5:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = ##134744072
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = vsplat(r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <32 x i32> undef, i32 134744072, i32 0
+ %v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <32 x i32> zeroinitializer
+ ret <32 x i32> %v1
+}
+
+; Splat register, 8-bit, v60
+define <128 x i8> @f6(i8 %a0) #0 {
+; CHECK-LABEL: f6:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = vsplatb(r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = vsplat(r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <128 x i8> undef, i8 %a0, i32 0
+ %v1 = shufflevector <128 x i8> %v0, <128 x i8> undef, <128 x i32> zeroinitializer
+ ret <128 x i8> %v1
+}
+
+; Splat register, 16 bit, v60
+define <64 x i16> @f7(i16 %a0) #0 {
+; CHECK-LABEL: f7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = combine(r0.l,r0.l)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = vsplat(r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <64 x i16> undef, i16 %a0, i32 0
+ %v1 = shufflevector <64 x i16> %v0, <64 x i16> undef, <64 x i32> zeroinitializer
+ ret <64 x i16> %v1
+}
+
+; Splat register, 32 bit, v60
+define <32 x i32> @f8(i32 %a0) #0 {
+; CHECK-LABEL: f8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = vsplat(r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <32 x i32> undef, i32 %a0, i32 0
+ %v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <32 x i32> zeroinitializer
+ ret <32 x i32> %v1
+}
+
+; Splat register, 8-bit, v62+
+define <128 x i8> @f9(i8 %a0) #1 {
+; CHECK-LABEL: f9:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: v0.b = vsplat(r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <128 x i8> undef, i8 %a0, i32 0
+ %v1 = shufflevector <128 x i8> %v0, <128 x i8> undef, <128 x i32> zeroinitializer
+ ret <128 x i8> %v1
+}
+
+; Splat register, 16 bit, v62+
+define <64 x i16> @f10(i16 %a0) #1 {
+; CHECK-LABEL: f10:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: v0.h = vsplat(r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <64 x i16> undef, i16 %a0, i32 0
+ %v1 = shufflevector <64 x i16> %v0, <64 x i16> undef, <64 x i32> zeroinitializer
+ ret <64 x i16> %v1
+}
+
+; Splat register, 32 bit, v62+
+define <32 x i32> @f11(i32 %a0) #1 {
+; CHECK-LABEL: f11:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = vsplat(r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <32 x i32> undef, i32 %a0, i32 0
+ %v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <32 x i32> zeroinitializer
+ ret <32 x i32> %v1
+}
+
+; Splat immediate, 8-bit, v60, pair
+define <256 x i8> @f12() #0 {
+; CHECK-LABEL: f12:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = ##2139062143
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v1 = vsplat(r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = v1
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <256 x i8> undef, i8 127, i32 0
+ %v1 = shufflevector <256 x i8> %v0, <256 x i8> undef, <256 x i32> zeroinitializer
+ ret <256 x i8> %v1
+}
+
+; Splat immediate, 16 bit, v60, pair
+define <128 x i16> @f13() #0 {
+; CHECK-LABEL: f13:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = ##-1437226411
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v1 = vsplat(r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = v1
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <128 x i16> undef, i16 43605, i32 0
+ %v1 = shufflevector <128 x i16> %v0, <128 x i16> undef, <128 x i32> zeroinitializer
+ ret <128 x i16> %v1
+}
+
+; Splat immediate, 32 bit, v60, pair
+define <64 x i32> @f14() #0 {
+; CHECK-LABEL: f14:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = ##134744072
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v1 = vsplat(r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = v1
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <64 x i32> undef, i32 134744072, i32 0
+ %v1 = shufflevector <64 x i32> %v0, <64 x i32> undef, <64 x i32> zeroinitializer
+ ret <64 x i32> %v1
+}
+
+; Splat immediate, 8-bit, v62+, pair
+define <256 x i8> @f15() #1 {
+; CHECK-LABEL: f15:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = #127
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v1.b = vsplat(r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = v1
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <256 x i8> undef, i8 127, i32 0
+ %v1 = shufflevector <256 x i8> %v0, <256 x i8> undef, <256 x i32> zeroinitializer
+ ret <256 x i8> %v1
+}
+
+; Splat immediate, 16 bit, v62+, pair
+define <128 x i16> @f16() #1 {
+; CHECK-LABEL: f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = #-21931
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v1.h = vsplat(r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = v1
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <128 x i16> undef, i16 43605, i32 0
+ %v1 = shufflevector <128 x i16> %v0, <128 x i16> undef, <128 x i32> zeroinitializer
+ ret <128 x i16> %v1
+}
+
+; Splat immediate, 32 bit, v62+, pair
+define <64 x i32> @f17() #1 {
+; CHECK-LABEL: f17:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = ##134744072
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v1 = vsplat(r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = v1
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <64 x i32> undef, i32 134744072, i32 0
+ %v1 = shufflevector <64 x i32> %v0, <64 x i32> undef, <64 x i32> zeroinitializer
+ ret <64 x i32> %v1
+}
+
+; Splat register, 8-bit, v60, pair
+define <256 x i8> @f18(i8 %a0) #0 {
+; CHECK-LABEL: f18:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = vsplatb(r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v1 = vsplat(r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = v1
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <256 x i8> undef, i8 %a0, i32 0
+ %v1 = shufflevector <256 x i8> %v0, <256 x i8> undef, <256 x i32> zeroinitializer
+ ret <256 x i8> %v1
+}
+
+; Splat register, 16 bit, v60, pair
+define <128 x i16> @f19(i16 %a0) #0 {
+; CHECK-LABEL: f19:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = combine(r0.l,r0.l)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v1 = vsplat(r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = v1
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <128 x i16> undef, i16 %a0, i32 0
+ %v1 = shufflevector <128 x i16> %v0, <128 x i16> undef, <128 x i32> zeroinitializer
+ ret <128 x i16> %v1
+}
+
+; Splat register, 32 bit, v60, pair
+define <64 x i32> @f20(i32 %a0) #0 {
+; CHECK-LABEL: f20:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: v1 = vsplat(r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = v1
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <64 x i32> undef, i32 %a0, i32 0
+ %v1 = shufflevector <64 x i32> %v0, <64 x i32> undef, <64 x i32> zeroinitializer
+ ret <64 x i32> %v1
+}
+
+; Splat register, 8-bit, v62+, pair
+define <256 x i8> @f21(i8 %a0) #1 {
+; CHECK-LABEL: f21:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: v1.b = vsplat(r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = v1
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <256 x i8> undef, i8 %a0, i32 0
+ %v1 = shufflevector <256 x i8> %v0, <256 x i8> undef, <256 x i32> zeroinitializer
+ ret <256 x i8> %v1
+}
+
+; Splat register, 16 bit, v62+, pair
+define <128 x i16> @f22(i16 %a0) #1 {
+; CHECK-LABEL: f22:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: v1.h = vsplat(r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = v1
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <128 x i16> undef, i16 %a0, i32 0
+ %v1 = shufflevector <128 x i16> %v0, <128 x i16> undef, <128 x i32> zeroinitializer
+ ret <128 x i16> %v1
+}
+
+; Splat register, 32 bit, v62+, pair
+define <64 x i32> @f23(i32 %a0) #1 {
+; CHECK-LABEL: f23:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: v1 = vsplat(r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = v1
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = insertelement <64 x i32> undef, i32 %a0, i32 0
+ %v1 = shufflevector <64 x i32> %v0, <64 x i32> undef, <64 x i32> zeroinitializer
+ ret <64 x i32> %v1
+}
+
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
+attributes #1 = { nounwind readnone "target-cpu"="hexagonv62" "target-features"="+hvxv62,+hvx-length128b" }
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