[PATCH] D89392: [GlobalISel] Fold unary opcodes in CSEMIRBuilder

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added reviewers: arsenm, aemerson, paquette, dsanders, qcolombet, volkan, aditya_nandakumar.
Herald added subscribers: llvm-commits, kerbowa, atanasyan, jrtc27, hiraditya, rovka, nhaehnle, jvesely, sdardis.
Herald added a project: LLVM.
foad requested review of this revision.
Herald added a subscriber: wdng.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D89392

Files:
  llvm/include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h
  llvm/include/llvm/CodeGen/GlobalISel/Utils.h
  llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
  llvm/lib/CodeGen/GlobalISel/Utils.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
  llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
  llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
  llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll
  llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
  llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
  llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir
  llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
  llvm/test/CodeGen/X86/GlobalISel/shl-scalar.ll
  llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir
  llvm/unittests/CodeGen/GlobalISel/ConstantFoldingTest.cpp