[PATCH] D88731: [AArch64] Combine UADDVs to generate vector add

[Vinay Madhusudan via Phabricator via llvm-commits]

mivnay added a comment.

In D88731#2328076 <https://reviews.llvm.org/D88731#2328076>, @dmgreen wrote:

> The pre-commit check is not being helpful here... :-/
>
> Seems like a useful optimisation to me though.
>
> Can you add test for i16 and i8. As far as I understand they will not fold because we will have legalized types and the return type will not match the vector element type?

Yes!

> We could think of doing this target independent instead. Folding add(vecreduce(x), vecreduce(y)) -> vecreduce(add(x, y)). It sounds generally useful to me. World that work in your case, or would it specifically need to work on UADDV?

I don't need to use UADDV specifically. But, I am not sure what impact it has on other targets (different lowerings, patterns, etc..).


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