[PATCH] D88731: [AArch64] Combine UADDVs to generate vector add

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

The pre-commit check is not being helpful here... :-/

Seems like a useful optimisation to me though.

Can you add test for i16 and i8. As far as I understand they will not fold because we will have legalized types and the return type will not match the vector element type? It's still worth having the tests. We could think of doing this target independent instead. Folding add(vecreduce(x), vecreduce(y)) -> vecreduce(add(x, y)). It sounds generally useful to me. World that work in your case, or would it specifically need to work on UADDV?

Can you also run the update_llc_test_checks.py script on the file and pre-commit the tests, just showing the changes here.



================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:12279
 
+// ADD(UADDV a, UADDV b) -->  UADDV((ADD a, b))
+static SDValue performUADDVCombine(SDNode *N,
----------------
--> UADDV(ADD a, b)


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:12281
+static SDValue performUADDVCombine(SDNode *N,
+                                   TargetLowering::DAGCombinerInfo &DCI,
+                                   SelectionDAG &DAG) {
----------------
You can get DAG from DCI.DAG (and I don't think think method uses DCI, which might simplify things).


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:12376
+  SDValue Val = performUADDVCombine(N, DCI, DAG);
+  if (Val.getNode()) {
+    return Val;
----------------
I think this can be:

  if (SDValue Val = performUADDVCombine(N, DCI, DAG))
    return Val;


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D88731/new/

https://reviews.llvm.org/D88731