[PATCH] D88742: [AArch64] Identify SAD pattern
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 13 00:21:14 PDT 2020
dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.
Thank you very much. With one little nitpick, LGTM.
================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:11092
+ // Check if vectors are of same type and valid size.
+ uint64_t size = VectorT1.getFixedSizeInBits();
+ if (VectorT1 != VectorT2 || (size != 64 && size != 128))
----------------
size -> Size
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D88742/new/
https://reviews.llvm.org/D88742
More information about the llvm-commits
mailing list