[PATCH] D89263: [SVE] Lower fixed length VECREDUCE_FADD operation

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally created this revision.
cameron.mcinally added reviewers: paulwalker-arm, kmclaughlin, efriedma.
Herald added subscribers: llvm-commits, psnobl, hiraditya, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.
cameron.mcinally requested review of this revision.

Nothing too controversial here. I did try something new with the 64b/128b vectors though. Here I picked SVE when there are more than 4 elements in the vector, and SVE for less. The motivation was to keep the instruction count down, but it could probably use some tuning to be sure. Thoughts on that?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D89263

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll

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