[PATCH] D89235: [SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0"
Paul Walker via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 12 04:40:57 PDT 2020
paulwalker-arm created this revision.
Herald added subscribers: llvm-commits, psnobl, hiraditya, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.
paulwalker-arm requested review of this revision.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D89235
Files:
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-insert-element.ll
Index: llvm/test/CodeGen/AArch64/sve-insert-element.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-insert-element.ll
+++ llvm/test/CodeGen/AArch64/sve-insert-element.ll
@@ -223,3 +223,57 @@
%d = insertelement <vscale x 16 x i8> %a, i8 %c, i32 3
ret <vscale x 16 x i8> %d
}
+
+define <vscale x 8 x half> @test_insert_into_undef_nxv8f16(half %a) {
+; CHECK-LABEL: test_insert_into_undef_nxv8f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0
+; CHECK-NEXT: ret
+ %b = insertelement <vscale x 8 x half> undef, half %a, i32 0
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 4 x half> @test_insert_into_undef_nxv4f16(half %a) {
+; CHECK-LABEL: test_insert_into_undef_nxv4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0
+; CHECK-NEXT: ret
+ %b = insertelement <vscale x 4 x half> undef, half %a, i32 0
+ ret <vscale x 4 x half> %b
+}
+
+define <vscale x 2 x half> @test_insert_into_undef_nxv2f16(half %a) {
+; CHECK-LABEL: test_insert_into_undef_nxv2f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0
+; CHECK-NEXT: ret
+ %b = insertelement <vscale x 2 x half> undef, half %a, i32 0
+ ret <vscale x 2 x half> %b
+}
+
+define <vscale x 4 x float> @test_insert_into_undef_nxv4f32(float %a) {
+; CHECK-LABEL: test_insert_into_undef_nxv4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0
+; CHECK-NEXT: ret
+ %b = insertelement <vscale x 4 x float> undef, float %a, i32 0
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 2 x float> @test_insert_into_undef_nxv2f32(float %a) {
+; CHECK-LABEL: test_insert_into_undef_nxv2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0
+; CHECK-NEXT: ret
+ %b = insertelement <vscale x 2 x float> undef, float %a, i32 0
+ ret <vscale x 2 x float> %b
+}
+
+define <vscale x 2 x double> @test_insert_into_undef_nxv2f64(double %a) {
+; CHECK-LABEL: test_insert_into_undef_nxv2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT: ret
+ %b = insertelement <vscale x 2 x double> undef, double %a, i32 0
+ ret <vscale x 2 x double> %b
+}
Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -2171,6 +2171,19 @@
def : Pat<(nxv2i64 (vector_insert (nxv2i64 (undef)), (i64 FPR64:$src), 0)),
(INSERT_SUBREG (nxv2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
+ def : Pat<(nxv8f16 (vector_insert (nxv8f16 (undef)), (f16 FPR16:$src), 0)),
+ (INSERT_SUBREG (nxv8f16 (IMPLICIT_DEF)), FPR16:$src, hsub)>;
+ def : Pat<(nxv4f16 (vector_insert (nxv4f16 (undef)), (f16 FPR16:$src), 0)),
+ (INSERT_SUBREG (nxv4f16 (IMPLICIT_DEF)), FPR16:$src, hsub)>;
+ def : Pat<(nxv2f16 (vector_insert (nxv2f16 (undef)), (f16 FPR16:$src), 0)),
+ (INSERT_SUBREG (nxv2f16 (IMPLICIT_DEF)), FPR16:$src, hsub)>;
+ def : Pat<(nxv4f32 (vector_insert (nxv4f32 (undef)), (f32 FPR32:$src), 0)),
+ (INSERT_SUBREG (nxv4f32 (IMPLICIT_DEF)), FPR32:$src, ssub)>;
+ def : Pat<(nxv2f32 (vector_insert (nxv2f32 (undef)), (f32 FPR32:$src), 0)),
+ (INSERT_SUBREG (nxv2f32 (IMPLICIT_DEF)), FPR32:$src, ssub)>;
+ def : Pat<(nxv2f64 (vector_insert (nxv2f64 (undef)), (f64 FPR64:$src), 0)),
+ (INSERT_SUBREG (nxv2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
+
// Insert scalar into vector[0]
def : Pat<(nxv16i8 (vector_insert (nxv16i8 ZPR:$vec), (i32 GPR32:$src), 0)),
(CPY_ZPmR_B ZPR:$vec, (PTRUE_B 1), GPR32:$src)>;
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