[PATCH] D89183: [VE] Add vector load/store instructions

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 added a comment.

Reply to an inline comment.



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Comment at: llvm/lib/Target/VE/VEISelLowering.cpp:637-672
+  addRegisterClass(MVT::v2i32, &VE::V64RegClass);
+  addRegisterClass(MVT::v4i32, &VE::V64RegClass);
+  addRegisterClass(MVT::v8i32, &VE::V64RegClass);
+  addRegisterClass(MVT::v16i32, &VE::V64RegClass);
+  addRegisterClass(MVT::v32i32, &VE::V64RegClass);
+  addRegisterClass(MVT::v64i32, &VE::V64RegClass);
+  addRegisterClass(MVT::v128i32, &VE::V64RegClass);
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simoll wrote:
> I wonder why there are vector types that do not map directly to vector registers.
Which types are not mapped as you are asked?  I think all vector types from v2f64 to v256f64 are mapped.


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https://reviews.llvm.org/D89183