[llvm] 6c32bc4 - [VE] Change to expand BRCOND
Kazushi Marukawa via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 12 03:18:46 PDT 2020
Author: Kazushi (Jam) Marukawa
Date: 2020-10-12T19:18:37+09:00
New Revision: 6c32bc4875117696d23c035e9e11320e095e52a0
URL: https://github.com/llvm/llvm-project/commit/6c32bc4875117696d23c035e9e11320e095e52a0
DIFF: https://github.com/llvm/llvm-project/commit/6c32bc4875117696d23c035e9e11320e095e52a0.diff
LOG: [VE] Change to expand BRCOND
VE doesn't have BRCOND instruction, so need to expand it. Also add
a regression test.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D89173
Added:
llvm/test/CodeGen/VE/brcond.ll
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index 79975f82f694..e0172a7b7a6d 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -679,6 +679,11 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
/// } Stack
+ /// Branch {
+ // VE doesn't have BRCOND
+ setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+ /// } Branch
+
/// Int Ops {
for (MVT IntVT : {MVT::i32, MVT::i64}) {
// VE has no REM or DIVREM operations.
diff --git a/llvm/test/CodeGen/VE/brcond.ll b/llvm/test/CodeGen/VE/brcond.ll
new file mode 100644
index 000000000000..515b6878c3ed
--- /dev/null
+++ b/llvm/test/CodeGen/VE/brcond.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+; Function Attrs: nounwind
+define void @test_then(i1 zeroext %0) {
+; CHECK-LABEL: test_then:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: breq.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ br i1 %0, label %2, label %3
+
+2: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %3
+
+3: ; preds = %2, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_else(i1 zeroext %0) {
+; CHECK-LABEL: test_else:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ br i1 %0, label %3, label %2
+
+2: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %3
+
+3: ; preds = %2, %1
+ ret void
+}
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