[llvm] f2e08c6 - [PowerPC] Add ppc32 funnel shift test coverage
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 10 10:20:31 PDT 2020
Author: Simon Pilgrim
Date: 2020-10-10T18:19:42+01:00
New Revision: f2e08c688e6c3223d14c4817c5ce0b55c03a8d1b
URL: https://github.com/llvm/llvm-project/commit/f2e08c688e6c3223d14c4817c5ce0b55c03a8d1b
DIFF: https://github.com/llvm/llvm-project/commit/f2e08c688e6c3223d14c4817c5ce0b55c03a8d1b.diff
LOG: [PowerPC] Add ppc32 funnel shift test coverage
Added:
Modified:
llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
llvm/test/CodeGen/PowerPC/funnel-shift.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll b/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
index d661dd56a065..d96b8518b98a 100644
--- a/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
+++ b/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
+; RUN: llc < %s -mtriple=ppc32-- | FileCheck %s --check-prefixes=CHECK,CHECK32
+; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s --check-prefixes=CHECK,CHECK64
declare i8 @llvm.fshl.i8(i8, i8, i8)
declare i16 @llvm.fshl.i16(i16, i16, i16)
@@ -27,10 +28,20 @@ define i8 @rotl_i8_const_shift(i8 %x) {
}
define i64 @rotl_i64_const_shift(i64 %x) {
-; CHECK-LABEL: rotl_i64_const_shift:
-; CHECK: # %bb.0:
-; CHECK-NEXT: rotldi 3, 3, 3
-; CHECK-NEXT: blr
+; CHECK32-LABEL: rotl_i64_const_shift:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: rotlwi 5, 4, 3
+; CHECK32-NEXT: rotlwi 6, 3, 3
+; CHECK32-NEXT: rlwimi 5, 3, 3, 0, 28
+; CHECK32-NEXT: rlwimi 6, 4, 3, 0, 28
+; CHECK32-NEXT: mr 3, 5
+; CHECK32-NEXT: mr 4, 6
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: rotl_i64_const_shift:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: rotldi 3, 3, 3
+; CHECK64-NEXT: blr
%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 3)
ret i64 %f
}
@@ -38,16 +49,27 @@ define i64 @rotl_i64_const_shift(i64 %x) {
; When first 2 operands match, it's a rotate (by variable amount).
define i16 @rotl_i16(i16 %x, i16 %z) {
-; CHECK-LABEL: rotl_i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: neg 5, 4
-; CHECK-NEXT: clrlwi 6, 3, 16
-; CHECK-NEXT: clrlwi 4, 4, 28
-; CHECK-NEXT: clrlwi 5, 5, 28
-; CHECK-NEXT: slw 3, 3, 4
-; CHECK-NEXT: srw 4, 6, 5
-; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: blr
+; CHECK32-LABEL: rotl_i16:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: clrlwi 6, 4, 28
+; CHECK32-NEXT: neg 4, 4
+; CHECK32-NEXT: clrlwi 5, 3, 16
+; CHECK32-NEXT: clrlwi 4, 4, 28
+; CHECK32-NEXT: slw 3, 3, 6
+; CHECK32-NEXT: srw 4, 5, 4
+; CHECK32-NEXT: or 3, 3, 4
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: rotl_i16:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: neg 5, 4
+; CHECK64-NEXT: clrlwi 6, 3, 16
+; CHECK64-NEXT: clrlwi 4, 4, 28
+; CHECK64-NEXT: clrlwi 5, 5, 28
+; CHECK64-NEXT: slw 3, 3, 4
+; CHECK64-NEXT: srw 4, 6, 5
+; CHECK64-NEXT: or 3, 3, 4
+; CHECK64-NEXT: blr
%f = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 %z)
ret i16 %f
}
@@ -62,10 +84,35 @@ define i32 @rotl_i32(i32 %x, i32 %z) {
}
define i64 @rotl_i64(i64 %x, i64 %z) {
-; CHECK-LABEL: rotl_i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: rotld 3, 3, 4
-; CHECK-NEXT: blr
+; CHECK32-LABEL: rotl_i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: clrlwi 5, 6, 26
+; CHECK32-NEXT: subfic 8, 5, 32
+; CHECK32-NEXT: neg 6, 6
+; CHECK32-NEXT: slw 7, 3, 5
+; CHECK32-NEXT: addi 9, 5, -32
+; CHECK32-NEXT: srw 8, 4, 8
+; CHECK32-NEXT: clrlwi 6, 6, 26
+; CHECK32-NEXT: slw 9, 4, 9
+; CHECK32-NEXT: or 7, 7, 8
+; CHECK32-NEXT: subfic 8, 6, 32
+; CHECK32-NEXT: or 7, 7, 9
+; CHECK32-NEXT: addi 9, 6, -32
+; CHECK32-NEXT: slw 8, 3, 8
+; CHECK32-NEXT: srw 9, 3, 9
+; CHECK32-NEXT: srw 3, 3, 6
+; CHECK32-NEXT: srw 6, 4, 6
+; CHECK32-NEXT: or 6, 6, 8
+; CHECK32-NEXT: or 6, 6, 9
+; CHECK32-NEXT: slw 4, 4, 5
+; CHECK32-NEXT: or 3, 7, 3
+; CHECK32-NEXT: or 4, 4, 6
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: rotl_i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: rotld 3, 3, 4
+; CHECK64-NEXT: blr
%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
ret i64 %f
}
@@ -73,10 +120,18 @@ define i64 @rotl_i64(i64 %x, i64 %z) {
; Vector rotate.
define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
-; CHECK-LABEL: rotl_v4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vrlw 2, 2, 3
-; CHECK-NEXT: blr
+; CHECK32-LABEL: rotl_v4i32:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: rotlw 3, 3, 7
+; CHECK32-NEXT: rotlw 4, 4, 8
+; CHECK32-NEXT: rotlw 5, 5, 9
+; CHECK32-NEXT: rotlw 6, 6, 10
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: rotl_v4i32:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: vrlw 2, 2, 3
+; CHECK64-NEXT: blr
%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
ret <4 x i32> %f
}
@@ -84,11 +139,19 @@ define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
; Vector rotate by constant splat amount.
define <4 x i32> @rotl_v4i32_const_shift(<4 x i32> %x) {
-; CHECK-LABEL: rotl_v4i32_const_shift:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vspltisw 3, 3
-; CHECK-NEXT: vrlw 2, 2, 3
-; CHECK-NEXT: blr
+; CHECK32-LABEL: rotl_v4i32_const_shift:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: rotlwi 3, 3, 3
+; CHECK32-NEXT: rotlwi 4, 4, 3
+; CHECK32-NEXT: rotlwi 5, 5, 3
+; CHECK32-NEXT: rotlwi 6, 6, 3
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: rotl_v4i32_const_shift:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: vspltisw 3, 3
+; CHECK64-NEXT: vrlw 2, 2, 3
+; CHECK64-NEXT: blr
%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
ret <4 x i32> %f
}
@@ -118,16 +181,27 @@ define i32 @rotr_i32_const_shift(i32 %x) {
; When first 2 operands match, it's a rotate (by variable amount).
define i16 @rotr_i16(i16 %x, i16 %z) {
-; CHECK-LABEL: rotr_i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: neg 5, 4
-; CHECK-NEXT: clrlwi 6, 3, 16
-; CHECK-NEXT: clrlwi 4, 4, 28
-; CHECK-NEXT: clrlwi 5, 5, 28
-; CHECK-NEXT: srw 4, 6, 4
-; CHECK-NEXT: slw 3, 3, 5
-; CHECK-NEXT: or 3, 4, 3
-; CHECK-NEXT: blr
+; CHECK32-LABEL: rotr_i16:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: clrlwi 6, 4, 28
+; CHECK32-NEXT: neg 4, 4
+; CHECK32-NEXT: clrlwi 5, 3, 16
+; CHECK32-NEXT: clrlwi 4, 4, 28
+; CHECK32-NEXT: srw 5, 5, 6
+; CHECK32-NEXT: slw 3, 3, 4
+; CHECK32-NEXT: or 3, 5, 3
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: rotr_i16:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: neg 5, 4
+; CHECK64-NEXT: clrlwi 6, 3, 16
+; CHECK64-NEXT: clrlwi 4, 4, 28
+; CHECK64-NEXT: clrlwi 5, 5, 28
+; CHECK64-NEXT: srw 4, 6, 4
+; CHECK64-NEXT: slw 3, 3, 5
+; CHECK64-NEXT: or 3, 4, 3
+; CHECK64-NEXT: blr
%f = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %z)
ret i16 %f
}
@@ -143,11 +217,36 @@ define i32 @rotr_i32(i32 %x, i32 %z) {
}
define i64 @rotr_i64(i64 %x, i64 %z) {
-; CHECK-LABEL: rotr_i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: neg 4, 4
-; CHECK-NEXT: rotld 3, 3, 4
-; CHECK-NEXT: blr
+; CHECK32-LABEL: rotr_i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: clrlwi 5, 6, 26
+; CHECK32-NEXT: subfic 8, 5, 32
+; CHECK32-NEXT: neg 6, 6
+; CHECK32-NEXT: srw 7, 4, 5
+; CHECK32-NEXT: addi 9, 5, -32
+; CHECK32-NEXT: slw 8, 3, 8
+; CHECK32-NEXT: clrlwi 6, 6, 26
+; CHECK32-NEXT: srw 9, 3, 9
+; CHECK32-NEXT: or 7, 7, 8
+; CHECK32-NEXT: subfic 8, 6, 32
+; CHECK32-NEXT: or 7, 7, 9
+; CHECK32-NEXT: addi 9, 6, -32
+; CHECK32-NEXT: srw 8, 4, 8
+; CHECK32-NEXT: slw 9, 4, 9
+; CHECK32-NEXT: slw 4, 4, 6
+; CHECK32-NEXT: slw 6, 3, 6
+; CHECK32-NEXT: or 6, 6, 8
+; CHECK32-NEXT: or 6, 6, 9
+; CHECK32-NEXT: srw 3, 3, 5
+; CHECK32-NEXT: or 4, 7, 4
+; CHECK32-NEXT: or 3, 3, 6
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: rotr_i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: neg 4, 4
+; CHECK64-NEXT: rotld 3, 3, 4
+; CHECK64-NEXT: blr
%f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z)
ret i64 %f
}
@@ -155,12 +254,24 @@ define i64 @rotr_i64(i64 %x, i64 %z) {
; Vector rotate.
define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
-; CHECK-LABEL: rotr_v4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xxlxor 36, 36, 36
-; CHECK-NEXT: vsubuwm 3, 4, 3
-; CHECK-NEXT: vrlw 2, 2, 3
-; CHECK-NEXT: blr
+; CHECK32-LABEL: rotr_v4i32:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: neg 7, 7
+; CHECK32-NEXT: neg 8, 8
+; CHECK32-NEXT: neg 9, 9
+; CHECK32-NEXT: neg 10, 10
+; CHECK32-NEXT: rotlw 3, 3, 7
+; CHECK32-NEXT: rotlw 4, 4, 8
+; CHECK32-NEXT: rotlw 5, 5, 9
+; CHECK32-NEXT: rotlw 6, 6, 10
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: rotr_v4i32:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: xxlxor 36, 36, 36
+; CHECK64-NEXT: vsubuwm 3, 4, 3
+; CHECK64-NEXT: vrlw 2, 2, 3
+; CHECK64-NEXT: blr
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
ret <4 x i32> %f
}
@@ -168,13 +279,21 @@ define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
; Vector rotate by constant splat amount.
define <4 x i32> @rotr_v4i32_const_shift(<4 x i32> %x) {
-; CHECK-LABEL: rotr_v4i32_const_shift:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vspltisw 3, -16
-; CHECK-NEXT: vspltisw 4, 13
-; CHECK-NEXT: vsubuwm 3, 4, 3
-; CHECK-NEXT: vrlw 2, 2, 3
-; CHECK-NEXT: blr
+; CHECK32-LABEL: rotr_v4i32_const_shift:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: rotlwi 3, 3, 29
+; CHECK32-NEXT: rotlwi 4, 4, 29
+; CHECK32-NEXT: rotlwi 5, 5, 29
+; CHECK32-NEXT: rotlwi 6, 6, 29
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: rotr_v4i32_const_shift:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: vspltisw 3, -16
+; CHECK64-NEXT: vspltisw 4, 13
+; CHECK64-NEXT: vsubuwm 3, 4, 3
+; CHECK64-NEXT: vrlw 2, 2, 3
+; CHECK64-NEXT: blr
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
ret <4 x i32> %f
}
diff --git a/llvm/test/CodeGen/PowerPC/funnel-shift.ll b/llvm/test/CodeGen/PowerPC/funnel-shift.ll
index 66be4606ada2..dd28b475ebd2 100644
--- a/llvm/test/CodeGen/PowerPC/funnel-shift.ll
+++ b/llvm/test/CodeGen/PowerPC/funnel-shift.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
+; RUN: llc < %s -mtriple=ppc32-- | FileCheck %s --check-prefixes=CHECK,CHECK32
+; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s --check-prefixes=CHECK,CHECK64
declare i8 @llvm.fshl.i8(i8, i8, i8)
declare i16 @llvm.fshl.i16(i16, i16, i16)
@@ -16,27 +17,64 @@ declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
; General case - all operands can be variables.
define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) {
-; CHECK-LABEL: fshl_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 5, 5, 27
-; CHECK-NEXT: subfic 6, 5, 32
-; CHECK-NEXT: slw 3, 3, 5
-; CHECK-NEXT: srw 4, 4, 6
-; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: blr
+; CHECK32-LABEL: fshl_i32:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: clrlwi 5, 5, 27
+; CHECK32-NEXT: slw 3, 3, 5
+; CHECK32-NEXT: subfic 5, 5, 32
+; CHECK32-NEXT: srw 4, 4, 5
+; CHECK32-NEXT: or 3, 3, 4
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: fshl_i32:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: clrlwi 5, 5, 27
+; CHECK64-NEXT: subfic 6, 5, 32
+; CHECK64-NEXT: slw 3, 3, 5
+; CHECK64-NEXT: srw 4, 4, 6
+; CHECK64-NEXT: or 3, 3, 4
+; CHECK64-NEXT: blr
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
ret i32 %f
}
define i64 @fshl_i64(i64 %x, i64 %y, i64 %z) {
-; CHECK-LABEL: fshl_i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 5, 5, 26
-; CHECK-NEXT: subfic 6, 5, 64
-; CHECK-NEXT: sld 3, 3, 5
-; CHECK-NEXT: srd 4, 4, 6
-; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: blr
+; CHECK32-LABEL: fshl_i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: clrlwi 7, 8, 26
+; CHECK32-NEXT: not 8, 8
+; CHECK32-NEXT: rotlwi 6, 6, 31
+; CHECK32-NEXT: subfic 10, 7, 32
+; CHECK32-NEXT: srwi 9, 5, 1
+; CHECK32-NEXT: slw 3, 3, 7
+; CHECK32-NEXT: clrlwi 8, 8, 26
+; CHECK32-NEXT: rlwimi 6, 5, 31, 0, 0
+; CHECK32-NEXT: srw 5, 4, 10
+; CHECK32-NEXT: srw 10, 9, 8
+; CHECK32-NEXT: srw 6, 6, 8
+; CHECK32-NEXT: or 3, 3, 5
+; CHECK32-NEXT: subfic 5, 8, 32
+; CHECK32-NEXT: addi 8, 8, -32
+; CHECK32-NEXT: slw 5, 9, 5
+; CHECK32-NEXT: srw 8, 9, 8
+; CHECK32-NEXT: addi 9, 7, -32
+; CHECK32-NEXT: slw 9, 4, 9
+; CHECK32-NEXT: or 5, 6, 5
+; CHECK32-NEXT: or 3, 3, 9
+; CHECK32-NEXT: or 5, 5, 8
+; CHECK32-NEXT: slw 4, 4, 7
+; CHECK32-NEXT: or 3, 3, 10
+; CHECK32-NEXT: or 4, 4, 5
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: fshl_i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: clrlwi 5, 5, 26
+; CHECK64-NEXT: subfic 6, 5, 64
+; CHECK64-NEXT: sld 3, 3, 5
+; CHECK64-NEXT: srd 4, 4, 6
+; CHECK64-NEXT: or 3, 3, 4
+; CHECK64-NEXT: blr
%f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 %z)
ret i64 %f
}
@@ -44,24 +82,81 @@ define i64 @fshl_i64(i64 %x, i64 %y, i64 %z) {
; Verify that weird types are minimally supported.
declare i37 @llvm.fshl.i37(i37, i37, i37)
define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
-; CHECK-LABEL: fshl_i37:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lis 6, -8857
-; CHECK-NEXT: sldi 4, 4, 27
-; CHECK-NEXT: ori 6, 6, 51366
-; CHECK-NEXT: sldi 6, 6, 32
-; CHECK-NEXT: oris 6, 6, 3542
-; CHECK-NEXT: ori 6, 6, 31883
-; CHECK-NEXT: mulhdu 6, 5, 6
-; CHECK-NEXT: rldicl 6, 6, 59, 5
-; CHECK-NEXT: mulli 6, 6, 37
-; CHECK-NEXT: sub 5, 5, 6
-; CHECK-NEXT: clrlwi 5, 5, 26
-; CHECK-NEXT: subfic 6, 5, 64
-; CHECK-NEXT: sld 3, 3, 5
-; CHECK-NEXT: srd 4, 4, 6
-; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: blr
+; CHECK32-LABEL: fshl_i37:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: mflr 0
+; CHECK32-NEXT: stw 0, 4(1)
+; CHECK32-NEXT: stwu 1, -32(1)
+; CHECK32-NEXT: .cfi_def_cfa_offset 32
+; CHECK32-NEXT: .cfi_offset lr, 4
+; CHECK32-NEXT: .cfi_offset r27, -20
+; CHECK32-NEXT: .cfi_offset r28, -16
+; CHECK32-NEXT: .cfi_offset r29, -12
+; CHECK32-NEXT: .cfi_offset r30, -8
+; CHECK32-NEXT: stw 27, 12(1) # 4-byte Folded Spill
+; CHECK32-NEXT: mr 27, 3
+; CHECK32-NEXT: stw 28, 16(1) # 4-byte Folded Spill
+; CHECK32-NEXT: mr 28, 4
+; CHECK32-NEXT: stw 29, 20(1) # 4-byte Folded Spill
+; CHECK32-NEXT: mr 29, 5
+; CHECK32-NEXT: stw 30, 24(1) # 4-byte Folded Spill
+; CHECK32-NEXT: mr 30, 6
+; CHECK32-NEXT: mr 3, 7
+; CHECK32-NEXT: mr 4, 8
+; CHECK32-NEXT: li 5, 0
+; CHECK32-NEXT: li 6, 37
+; CHECK32-NEXT: bl __umoddi3
+; CHECK32-NEXT: clrlwi 6, 4, 26
+; CHECK32-NEXT: srwi 3, 30, 6
+; CHECK32-NEXT: not 4, 4
+; CHECK32-NEXT: subfic 8, 6, 32
+; CHECK32-NEXT: slwi 5, 30, 26
+; CHECK32-NEXT: rlwimi 3, 29, 26, 1, 5
+; CHECK32-NEXT: slw 7, 27, 6
+; CHECK32-NEXT: clrlwi 4, 4, 26
+; CHECK32-NEXT: srw 8, 28, 8
+; CHECK32-NEXT: srw 9, 3, 4
+; CHECK32-NEXT: srw 5, 5, 4
+; CHECK32-NEXT: or 7, 7, 8
+; CHECK32-NEXT: subfic 8, 4, 32
+; CHECK32-NEXT: addi 4, 4, -32
+; CHECK32-NEXT: slw 8, 3, 8
+; CHECK32-NEXT: srw 4, 3, 4
+; CHECK32-NEXT: addi 3, 6, -32
+; CHECK32-NEXT: slw 3, 28, 3
+; CHECK32-NEXT: or 5, 5, 8
+; CHECK32-NEXT: or 3, 7, 3
+; CHECK32-NEXT: or 4, 5, 4
+; CHECK32-NEXT: slw 5, 28, 6
+; CHECK32-NEXT: or 3, 3, 9
+; CHECK32-NEXT: or 4, 5, 4
+; CHECK32-NEXT: lwz 30, 24(1) # 4-byte Folded Reload
+; CHECK32-NEXT: lwz 29, 20(1) # 4-byte Folded Reload
+; CHECK32-NEXT: lwz 28, 16(1) # 4-byte Folded Reload
+; CHECK32-NEXT: lwz 27, 12(1) # 4-byte Folded Reload
+; CHECK32-NEXT: lwz 0, 36(1)
+; CHECK32-NEXT: addi 1, 1, 32
+; CHECK32-NEXT: mtlr 0
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: fshl_i37:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: lis 6, -8857
+; CHECK64-NEXT: sldi 4, 4, 27
+; CHECK64-NEXT: ori 6, 6, 51366
+; CHECK64-NEXT: sldi 6, 6, 32
+; CHECK64-NEXT: oris 6, 6, 3542
+; CHECK64-NEXT: ori 6, 6, 31883
+; CHECK64-NEXT: mulhdu 6, 5, 6
+; CHECK64-NEXT: rldicl 6, 6, 59, 5
+; CHECK64-NEXT: mulli 6, 6, 37
+; CHECK64-NEXT: sub 5, 5, 6
+; CHECK64-NEXT: clrlwi 5, 5, 26
+; CHECK64-NEXT: subfic 6, 5, 64
+; CHECK64-NEXT: sld 3, 3, 5
+; CHECK64-NEXT: srd 4, 4, 6
+; CHECK64-NEXT: or 3, 3, 4
+; CHECK64-NEXT: blr
%f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
ret i37 %f
}
@@ -107,12 +202,21 @@ define i32 @fshl_i32_const_overshift(i32 %x, i32 %y) {
; 64-bit should also work.
define i64 @fshl_i64_const_overshift(i64 %x, i64 %y) {
-; CHECK-LABEL: fshl_i64_const_overshift:
-; CHECK: # %bb.0:
-; CHECK-NEXT: rotldi 4, 4, 41
-; CHECK-NEXT: rldimi 4, 3, 41, 0
-; CHECK-NEXT: mr 3, 4
-; CHECK-NEXT: blr
+; CHECK32-LABEL: fshl_i64_const_overshift:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: rotlwi 6, 6, 9
+; CHECK32-NEXT: rotlwi 3, 5, 9
+; CHECK32-NEXT: rlwimi 6, 5, 9, 0, 22
+; CHECK32-NEXT: rlwimi 3, 4, 9, 0, 22
+; CHECK32-NEXT: mr 4, 6
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: fshl_i64_const_overshift:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: rotldi 4, 4, 41
+; CHECK64-NEXT: rldimi 4, 3, 41, 0
+; CHECK64-NEXT: mr 3, 4
+; CHECK64-NEXT: blr
%f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 105)
ret i64 %f
}
@@ -133,27 +237,64 @@ define i8 @fshl_i8_const_fold() {
; General case - all operands can be variables.
define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) {
-; CHECK-LABEL: fshr_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 5, 5, 27
-; CHECK-NEXT: subfic 6, 5, 32
-; CHECK-NEXT: srw 4, 4, 5
-; CHECK-NEXT: slw 3, 3, 6
-; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: blr
+; CHECK32-LABEL: fshr_i32:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: clrlwi 5, 5, 27
+; CHECK32-NEXT: srw 4, 4, 5
+; CHECK32-NEXT: subfic 5, 5, 32
+; CHECK32-NEXT: slw 3, 3, 5
+; CHECK32-NEXT: or 3, 3, 4
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: fshr_i32:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: clrlwi 5, 5, 27
+; CHECK64-NEXT: subfic 6, 5, 32
+; CHECK64-NEXT: srw 4, 4, 5
+; CHECK64-NEXT: slw 3, 3, 6
+; CHECK64-NEXT: or 3, 3, 4
+; CHECK64-NEXT: blr
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
ret i32 %f
}
define i64 @fshr_i64(i64 %x, i64 %y, i64 %z) {
-; CHECK-LABEL: fshr_i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 5, 5, 26
-; CHECK-NEXT: subfic 6, 5, 64
-; CHECK-NEXT: srd 4, 4, 5
-; CHECK-NEXT: sld 3, 3, 6
-; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: blr
+; CHECK32-LABEL: fshr_i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: clrlwi 7, 8, 26
+; CHECK32-NEXT: slwi 9, 4, 1
+; CHECK32-NEXT: not 8, 8
+; CHECK32-NEXT: rotlwi 4, 4, 1
+; CHECK32-NEXT: subfic 10, 7, 32
+; CHECK32-NEXT: srw 6, 6, 7
+; CHECK32-NEXT: clrlwi 8, 8, 26
+; CHECK32-NEXT: rlwimi 4, 3, 1, 0, 30
+; CHECK32-NEXT: slw 3, 5, 10
+; CHECK32-NEXT: slw 10, 9, 8
+; CHECK32-NEXT: slw 4, 4, 8
+; CHECK32-NEXT: or 3, 6, 3
+; CHECK32-NEXT: subfic 6, 8, 32
+; CHECK32-NEXT: addi 8, 8, -32
+; CHECK32-NEXT: srw 6, 9, 6
+; CHECK32-NEXT: slw 8, 9, 8
+; CHECK32-NEXT: addi 9, 7, -32
+; CHECK32-NEXT: srw 9, 5, 9
+; CHECK32-NEXT: or 3, 3, 9
+; CHECK32-NEXT: or 6, 4, 6
+; CHECK32-NEXT: or 4, 10, 3
+; CHECK32-NEXT: or 3, 6, 8
+; CHECK32-NEXT: srw 5, 5, 7
+; CHECK32-NEXT: or 3, 3, 5
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: fshr_i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: clrlwi 5, 5, 26
+; CHECK64-NEXT: subfic 6, 5, 64
+; CHECK64-NEXT: srd 4, 4, 5
+; CHECK64-NEXT: sld 3, 3, 6
+; CHECK64-NEXT: or 3, 3, 4
+; CHECK64-NEXT: blr
%f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 %z)
ret i64 %f
}
@@ -161,25 +302,86 @@ define i64 @fshr_i64(i64 %x, i64 %y, i64 %z) {
; Verify that weird types are minimally supported.
declare i37 @llvm.fshr.i37(i37, i37, i37)
define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
-; CHECK-LABEL: fshr_i37:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lis 6, -8857
-; CHECK-NEXT: sldi 4, 4, 27
-; CHECK-NEXT: ori 6, 6, 51366
-; CHECK-NEXT: sldi 6, 6, 32
-; CHECK-NEXT: oris 6, 6, 3542
-; CHECK-NEXT: ori 6, 6, 31883
-; CHECK-NEXT: mulhdu 6, 5, 6
-; CHECK-NEXT: rldicl 6, 6, 59, 5
-; CHECK-NEXT: mulli 6, 6, 37
-; CHECK-NEXT: sub 5, 5, 6
-; CHECK-NEXT: addi 5, 5, 27
-; CHECK-NEXT: clrlwi 5, 5, 26
-; CHECK-NEXT: subfic 6, 5, 64
-; CHECK-NEXT: srd 4, 4, 5
-; CHECK-NEXT: sld 3, 3, 6
-; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: blr
+; CHECK32-LABEL: fshr_i37:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: mflr 0
+; CHECK32-NEXT: stw 0, 4(1)
+; CHECK32-NEXT: stwu 1, -32(1)
+; CHECK32-NEXT: .cfi_def_cfa_offset 32
+; CHECK32-NEXT: .cfi_offset lr, 4
+; CHECK32-NEXT: .cfi_offset r27, -20
+; CHECK32-NEXT: .cfi_offset r28, -16
+; CHECK32-NEXT: .cfi_offset r29, -12
+; CHECK32-NEXT: .cfi_offset r30, -8
+; CHECK32-NEXT: stw 27, 12(1) # 4-byte Folded Spill
+; CHECK32-NEXT: mr 27, 3
+; CHECK32-NEXT: stw 28, 16(1) # 4-byte Folded Spill
+; CHECK32-NEXT: mr 28, 4
+; CHECK32-NEXT: stw 29, 20(1) # 4-byte Folded Spill
+; CHECK32-NEXT: mr 29, 5
+; CHECK32-NEXT: stw 30, 24(1) # 4-byte Folded Spill
+; CHECK32-NEXT: mr 30, 6
+; CHECK32-NEXT: mr 3, 7
+; CHECK32-NEXT: mr 4, 8
+; CHECK32-NEXT: li 5, 0
+; CHECK32-NEXT: li 6, 37
+; CHECK32-NEXT: bl __umoddi3
+; CHECK32-NEXT: addi 4, 4, 27
+; CHECK32-NEXT: rotlwi 5, 30, 27
+; CHECK32-NEXT: clrlwi 8, 4, 26
+; CHECK32-NEXT: slwi 3, 30, 27
+; CHECK32-NEXT: rotlwi 7, 28, 1
+; CHECK32-NEXT: rlwimi 5, 29, 27, 0, 4
+; CHECK32-NEXT: not 4, 4
+; CHECK32-NEXT: subfic 9, 8, 32
+; CHECK32-NEXT: slwi 6, 28, 1
+; CHECK32-NEXT: rlwimi 7, 27, 1, 0, 30
+; CHECK32-NEXT: srw 3, 3, 8
+; CHECK32-NEXT: clrlwi 4, 4, 26
+; CHECK32-NEXT: slw 9, 5, 9
+; CHECK32-NEXT: slw 10, 6, 4
+; CHECK32-NEXT: slw 7, 7, 4
+; CHECK32-NEXT: or 3, 3, 9
+; CHECK32-NEXT: subfic 9, 4, 32
+; CHECK32-NEXT: addi 4, 4, -32
+; CHECK32-NEXT: srw 9, 6, 9
+; CHECK32-NEXT: slw 6, 6, 4
+; CHECK32-NEXT: addi 4, 8, -32
+; CHECK32-NEXT: srw 4, 5, 4
+; CHECK32-NEXT: or 3, 3, 4
+; CHECK32-NEXT: or 7, 7, 9
+; CHECK32-NEXT: or 4, 10, 3
+; CHECK32-NEXT: or 3, 7, 6
+; CHECK32-NEXT: srw 5, 5, 8
+; CHECK32-NEXT: or 3, 3, 5
+; CHECK32-NEXT: lwz 30, 24(1) # 4-byte Folded Reload
+; CHECK32-NEXT: lwz 29, 20(1) # 4-byte Folded Reload
+; CHECK32-NEXT: lwz 28, 16(1) # 4-byte Folded Reload
+; CHECK32-NEXT: lwz 27, 12(1) # 4-byte Folded Reload
+; CHECK32-NEXT: lwz 0, 36(1)
+; CHECK32-NEXT: addi 1, 1, 32
+; CHECK32-NEXT: mtlr 0
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: fshr_i37:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: lis 6, -8857
+; CHECK64-NEXT: sldi 4, 4, 27
+; CHECK64-NEXT: ori 6, 6, 51366
+; CHECK64-NEXT: sldi 6, 6, 32
+; CHECK64-NEXT: oris 6, 6, 3542
+; CHECK64-NEXT: ori 6, 6, 31883
+; CHECK64-NEXT: mulhdu 6, 5, 6
+; CHECK64-NEXT: rldicl 6, 6, 59, 5
+; CHECK64-NEXT: mulli 6, 6, 37
+; CHECK64-NEXT: sub 5, 5, 6
+; CHECK64-NEXT: addi 5, 5, 27
+; CHECK64-NEXT: clrlwi 5, 5, 26
+; CHECK64-NEXT: subfic 6, 5, 64
+; CHECK64-NEXT: srd 4, 4, 5
+; CHECK64-NEXT: sld 3, 3, 6
+; CHECK64-NEXT: or 3, 3, 4
+; CHECK64-NEXT: blr
%f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)
ret i37 %f
}
@@ -225,12 +427,22 @@ define i32 @fshr_i32_const_overshift(i32 %x, i32 %y) {
; 64-bit should also work. 105-64 = 41.
define i64 @fshr_i64_const_overshift(i64 %x, i64 %y) {
-; CHECK-LABEL: fshr_i64_const_overshift:
-; CHECK: # %bb.0:
-; CHECK-NEXT: rotldi 4, 4, 23
-; CHECK-NEXT: rldimi 4, 3, 23, 0
-; CHECK-NEXT: mr 3, 4
-; CHECK-NEXT: blr
+; CHECK32-LABEL: fshr_i64_const_overshift:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: rotlwi 6, 4, 23
+; CHECK32-NEXT: rotlwi 5, 5, 23
+; CHECK32-NEXT: rlwimi 6, 3, 23, 0, 8
+; CHECK32-NEXT: rlwimi 5, 4, 23, 0, 8
+; CHECK32-NEXT: mr 3, 6
+; CHECK32-NEXT: mr 4, 5
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: fshr_i64_const_overshift:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: rotldi 4, 4, 23
+; CHECK64-NEXT: rldimi 4, 3, 23, 0
+; CHECK64-NEXT: mr 3, 4
+; CHECK64-NEXT: blr
%f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 105)
ret i64 %f
}
@@ -272,10 +484,18 @@ define <4 x i32> @fshl_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) {
}
define <4 x i32> @fshr_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) {
-; CHECK-LABEL: fshr_v4i32_shift_by_bitwidth:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmr 2, 3
-; CHECK-NEXT: blr
+; CHECK32-LABEL: fshr_v4i32_shift_by_bitwidth:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: mr 6, 10
+; CHECK32-NEXT: mr 5, 9
+; CHECK32-NEXT: mr 4, 8
+; CHECK32-NEXT: mr 3, 7
+; CHECK32-NEXT: blr
+;
+; CHECK64-LABEL: fshr_v4i32_shift_by_bitwidth:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: vmr 2, 3
+; CHECK64-NEXT: blr
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
ret <4 x i32> %f
}
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