[PATCH] D89173: [VE] Change to expand BRCOND

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 created this revision.
kaz7 added reviewers: simoll, k-ishizaka.
kaz7 added projects: LLVM, VE.
Herald added subscribers: llvm-commits, hiraditya.
kaz7 requested review of this revision.

VE doesn't have BRCOND instruction, so need to expand it.  Also add
a regression test.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D89173

Files:
  llvm/lib/Target/VE/VEISelLowering.cpp
  llvm/test/CodeGen/VE/brcond.ll


Index: llvm/test/CodeGen/VE/brcond.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/VE/brcond.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+; Function Attrs: nounwind
+define void @test_then(i1 zeroext %0) {
+; CHECK-LABEL: test_then:
+; CHECK:       .LBB{{[0-9]+}}_4:
+; CHECK-NEXT:    breq.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s11, 0, %s9
+  br i1 %0, label %2, label %3
+
+2:                                                ; preds = %1
+  tail call void asm sideeffect "nop", ""()
+  br label %3
+
+3:                                                ; preds = %2, %1
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @test_else(i1 zeroext %0) {
+; CHECK-LABEL: test_else:
+; CHECK:       .LBB{{[0-9]+}}_4:
+; CHECK-NEXT:    brne.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s11, 0, %s9
+  br i1 %0, label %3, label %2
+
+2:                                                ; preds = %1
+  tail call void asm sideeffect "nop", ""()
+  br label %3
+
+3:                                                ; preds = %2, %1
+  ret void
+}
Index: llvm/lib/Target/VE/VEISelLowering.cpp
===================================================================
--- llvm/lib/Target/VE/VEISelLowering.cpp
+++ llvm/lib/Target/VE/VEISelLowering.cpp
@@ -675,6 +675,11 @@
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
   /// } Stack
 
+  /// Branch {
+  // VE doesn't have BRCOND
+  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+  /// } Branch
+
   /// Int Ops {
   for (MVT IntVT : {MVT::i32, MVT::i64}) {
     // VE has no REM or DIVREM operations.


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