[PATCH] D89139: [DAG][RISCV] Improve funnel shift promotion to use 'double shift' patterns

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:1155
+    Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, HiShift);
+    Lo = DAG.getNode(ISD::AND, DL, VT, Lo, DAG.getConstant(Mask, DL, VT));
+    SDValue Res = DAG.getNode(ISD::OR, DL, VT, Hi, Lo);
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Can we use DAG.getZeroExtendInReg here with the old VT?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89139/new/

https://reviews.llvm.org/D89139