[PATCH] D88783: [InstCombine] matchFunnelShift - fold or(shl(a,x),lshr(b,sub(bw,x))) -> fshl(a,b,x) iff x < bw

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri accepted this revision.
lebedev.ri added a comment.
This revision is now accepted and ready to land.

Aha! I was confused for a moment whether that was info was one of those that does survive into the back-end, and it does:
https://godbolt.org/z/6MWecW

  SelectionDAG has 25 nodes:
    t0: ch = EntryToken
        t2: i32,ch = CopyFromReg t0, Register:i32 %0
        t4: i32,ch = CopyFromReg t0, Register:i32 %1
      t12: i64 = build_pair t2, t4
        t6: i32,ch = CopyFromReg t0, Register:i32 %2
        t8: i32,ch = CopyFromReg t0, Register:i32 %3
      t13: i64 = build_pair t6, t8
        t11: i32,ch = load<(load 4 from %fixed-stack.0)> t0, FrameIndex:i32<-1>, undef:i32
      t15: i64,ch = load<(load 8 from %ir.aptr, !range !0)> t0, t11, undef:i32
    t16: i64 = fshl t12, t13, t15
      t19: i32 = extract_element t16, Constant:i32<0>
    t21: ch,glue = CopyToReg t0, Register:i32 $r0, t19
      t18: i32 = extract_element t16, Constant:i32<1>
    t23: ch,glue = CopyToReg t21, Register:i32 $r1, t18, t21:1
    t24: ch = ARMISD::RET_FLAG t23, Register:i32 $r0, Register:i32 $r1, t23:1

So this seems fine to me.


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https://reviews.llvm.org/D88783