[PATCH] D89077: [AMDGPU] Run hazard recognizer pass later

Stanislav Mekhanoshin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 8 22:48:54 PDT 2020


rampitec added a comment.

In D89077#2320691 <https://reviews.llvm.org/D89077#2320691>, @t-tye wrote:

> In D89077#2320512 <https://reviews.llvm.org/D89077#2320512>, @kerbowa wrote:
>
>> In D89077#2320507 <https://reviews.llvm.org/D89077#2320507>, @t-tye wrote:
>>
>>> Is this now running after the waitcnt insertion pass? That would avoid the NOPs currently being inserted to split memory clauses that are not necessary as the waitcnt instructions will split the clauses.
>>
>> We also insert nops in the post-RA scheduler.
>
> In earlier conversation it was suggested that the spurious NOPs were explained as happening because the hazard recognizer inserted them to break memory clauses, and then the waitcnt pass ran. There would be no need to insert the NOPs if the waitcnt instructions were already there. So seems that was not a valid explanation, perhaps the post-RA scheduler is an explanation, but I am unclear why it put those ones in. @rampitec can you help explain?

Post-RA scheduler and hazard recognizer is the same pass if you run post-RA scheduler. If not it is a separate pass.


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