[PATCH] D89084: [PowerPC] Combine select_cc (x, 0, t, f, lt) to avoid generating `isel`
ChenZheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 8 22:15:29 PDT 2020
shchenz added a comment.
Thanks for doing this. This is what we should do for PPC target.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13624
+ DAG.getConstant(Shift, DL, VT));
+ return DAG.getNode(ISD::SUB, DL, VT, SDValue(SubOp, 0), Temp);
+ }
----------------
I think it is not a win transformation for the worst case?
```
li
li
cmp
select
```
VS
```
srl
ext
not
shl
sub
```
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D89084/new/
https://reviews.llvm.org/D89084
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