[llvm] 2c4c2dc - [MCRegister] Simplify isStackSlot & isPhysicalRegister and delete isPhysical. NFC
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 8 22:08:40 PDT 2020
Author: Fangrui Song
Date: 2020-10-08T22:08:33-07:00
New Revision: 2c4c2dc2d95aa7239cd59f8fa251fd336aeac87d
URL: https://github.com/llvm/llvm-project/commit/2c4c2dc2d95aa7239cd59f8fa251fd336aeac87d
DIFF: https://github.com/llvm/llvm-project/commit/2c4c2dc2d95aa7239cd59f8fa251fd336aeac87d.diff
LOG: [MCRegister] Simplify isStackSlot & isPhysicalRegister and delete isPhysical. NFC
Added:
Modified:
llvm/include/llvm/MC/MCRegister.h
llvm/lib/CodeGen/MachineBasicBlock.cpp
llvm/lib/CodeGen/MachineOperand.cpp
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/MC/MCRegister.h b/llvm/include/llvm/MC/MCRegister.h
index 21ffe28ef6a7..7300f343354a 100644
--- a/llvm/include/llvm/MC/MCRegister.h
+++ b/llvm/include/llvm/MC/MCRegister.h
@@ -47,21 +47,13 @@ class MCRegister {
/// Register::isStackSlot() for the more information on them.
///
static bool isStackSlot(unsigned Reg) {
- return !(Reg & VirtualRegFlag) &&
- uint32_t(Reg & ~VirtualRegFlag) >= FirstStackSlot;
+ return FirstStackSlot <= Reg && Reg < VirtualRegFlag;
}
/// Return true if the specified register number is in
/// the physical register namespace.
static bool isPhysicalRegister(unsigned Reg) {
- return Reg >= FirstPhysicalReg && !(Reg & VirtualRegFlag) &&
- !isStackSlot(Reg);
- }
-
- /// Return true if the specified register number is in the physical register
- /// namespace.
- bool isPhysical() const {
- return isPhysicalRegister(Reg);
+ return FirstPhysicalReg <= Reg && Reg < FirstStackSlot;
}
constexpr operator unsigned() const {
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 6272adcf114d..13ece5ed7d1c 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -583,7 +583,7 @@ void MachineBasicBlock::sortUniqueLiveIns() {
Register
MachineBasicBlock::addLiveIn(MCRegister PhysReg, const TargetRegisterClass *RC) {
assert(getParent() && "MBB must be inserted in function");
- assert(PhysReg.isPhysical() && "Expected physreg");
+ assert(Register::isPhysicalRegister(PhysReg) && "Expected physreg");
assert(RC && "Register class is required");
assert((isEHPad() || this == &getParent()->front()) &&
"Only the entry block and landing pads can have physreg live ins");
diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp
index 76b69dfdcf71..236ed3fb1968 100644
--- a/llvm/lib/CodeGen/MachineOperand.cpp
+++ b/llvm/lib/CodeGen/MachineOperand.cpp
@@ -85,7 +85,7 @@ void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
}
void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
- assert(Reg.isPhysical());
+ assert(Register::isPhysicalRegister(Reg));
if (getSubReg()) {
Reg = TRI.getSubReg(Reg, getSubReg());
// Note that getSubReg() may return 0 if the sub-register doesn't exist.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 9b6a7d096273..ed07c23716cc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2695,7 +2695,7 @@ bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B,
const TargetRegisterClass *ArgRC,
LLT ArgTy) const {
MCRegister SrcReg = Arg->getRegister();
- assert(SrcReg.isPhysical() && "Physical register expected");
+ assert(Register::isPhysicalRegister(SrcReg) && "Physical register expected");
assert(DstReg.isVirtual() && "Virtual register expected");
Register LiveIn = getFunctionLiveInPhysReg(B.getMF(), B.getTII(), SrcReg, *ArgRC,
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