[llvm] 8b6674e - [NFC][Test] Update the test with update_llc_test_checks.py
QingShan Zhang via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 8 19:26:57 PDT 2020
Author: QingShan Zhang
Date: 2020-10-09T02:26:03Z
New Revision: 8b6674e64f67f0d441045177f0033ef78e844fc4
URL: https://github.com/llvm/llvm-project/commit/8b6674e64f67f0d441045177f0033ef78e844fc4
DIFF: https://github.com/llvm/llvm-project/commit/8b6674e64f67f0d441045177f0033ef78e844fc4.diff
LOG: [NFC][Test] Update the test with update_llc_test_checks.py
Added:
Modified:
llvm/test/CodeGen/PowerPC/branch_coalesce.ll
llvm/test/CodeGen/PowerPC/f128-aggregates.ll
llvm/test/CodeGen/PowerPC/f128-passByValue.ll
llvm/test/CodeGen/PowerPC/ppcf128-endian.ll
llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
llvm/test/CodeGen/PowerPC/toc-float.ll
llvm/test/CodeGen/PowerPC/vec-itofp.ll
llvm/test/CodeGen/PowerPC/vec-trunc2.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/branch_coalesce.ll b/llvm/test/CodeGen/PowerPC/branch_coalesce.ll
index c0486015a3a3..5f9c4f380475 100644
--- a/llvm/test/CodeGen/PowerPC/branch_coalesce.ll
+++ b/llvm/test/CodeGen/PowerPC/branch_coalesce.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s
@@ -5,21 +6,21 @@
; Function Attrs: nounwind
define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
-
-; CHECK-LABEL: @testBranchCoal
-; CHECK: cmplwi 6, 0
-; CHECK: beq 0, .LBB[[LAB1:[0-9_]+]]
-; CHECK-DAG: addis [[LD1REG:[0-9]+]], 2, .LCPI0_0 at toc@ha
-; CHECK-DAG: addis [[LD2REG:[0-9]+]], 2, .LCPI0_1 at toc@ha
-; CHECK-DAG: xxlxor 2, 2, 2
-; CHECK-NOT: beq
-; CHECK-DAG: lfd 1, .LCPI0_0 at toc@l([[LD1REG]])
-; CHECK-DAG: lfd 3, .LCPI0_1 at toc@l([[LD2REG]])
-; CHECK: .LBB[[LAB1]]
-; CHECK: xsadddp 0, 1, 2
-; CHECK: xsadddp 1, 0, 3
-; CHECK: blr
-
+; CHECK-LABEL: testBranchCoal:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplwi 6, 0
+; CHECK-NEXT: beq 0, .LBB0_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: addis 3, 2, .LCPI0_0 at toc@ha
+; CHECK-NEXT: addis 4, 2, .LCPI0_1 at toc@ha
+; CHECK-NEXT: xxlxor 2, 2, 2
+; CHECK-NEXT: lfd 1, .LCPI0_0 at toc@l(3)
+; CHECK-NEXT: lfd 3, .LCPI0_1 at toc@l(4)
+; CHECK-NEXT: .LBB0_2: # %entry
+; CHECK-NEXT: xsadddp 0, 1, 2
+; CHECK-NEXT: xsadddp 1, 0, 3
+; CHECK-NEXT: blr
+;
; CHECK-NOCOALESCE-LABEL: testBranchCoal:
; CHECK-NOCOALESCE: # %bb.0: # %entry
; CHECK-NOCOALESCE-NEXT: cmplwi 6, 0
@@ -43,6 +44,7 @@ define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
; CHECK-NOCOALESCE-NEXT: xxlxor 2, 2, 2
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_3
; CHECK-NOCOALESCE-NEXT: b .LBB0_4
+
entry:
%test = icmp eq i32 %x, 0
diff --git a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll
index 956c30f7d8ec..58ed954bca54 100644
--- a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
; RUN: | FileCheck %s
@@ -18,10 +19,12 @@ define fp128 @testArray_01(fp128* nocapture readonly %sa) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 32(r3)
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testArray_01:
-; CHECK-BE: lxv v2, 32(r3)
-; CHECK-BE-NEXT: blr
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: lxv v2, 32(r3)
+; CHECK-BE-NEXT: blr
+
entry:
%arrayidx = getelementptr inbounds fp128, fp128* %sa, i64 2
%0 = load fp128, fp128* %arrayidx, align 16
@@ -36,10 +39,14 @@ define fp128 @testArray_02() {
; CHECK-NEXT: ld r3, .LC0 at toc@l(r3)
; CHECK-NEXT: lxv v2, 32(r3)
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testArray_02:
-; CHECK-BE: lxv v2, 32(r3)
-; CHECK-BE-NEXT: blr
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; CHECK-BE-NEXT: lxv v2, 32(r3)
+; CHECK-BE-NEXT: blr
+
entry:
%0 = load fp128, fp128* getelementptr inbounds ([3 x fp128], [3 x fp128]* @a1,
i64 0, i64 2), align 16
@@ -51,10 +58,11 @@ define fp128 @testStruct_01(fp128 inreg returned %a.coerce) {
; CHECK-LABEL: testStruct_01:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testStruct_01:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: blr
+; CHECK-BE-NEXT: blr
+
entry:
ret fp128 %a.coerce
}
@@ -65,10 +73,12 @@ define fp128 @testStruct_02([8 x fp128] %a.coerce) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmr v2, v9
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testStruct_02:
-; CHECK-BE: vmr v2, v9
-; CHECK-BE-NEXT: blr
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: vmr v2, v9
+; CHECK-BE-NEXT: blr
+
entry:
%a.coerce.fca.7.extract = extractvalue [8 x fp128] %a.coerce, 7
ret fp128 %a.coerce.fca.7.extract
@@ -77,33 +87,33 @@ entry:
; Since we can only pass a max of 8 float128 value in VSX registers, ensure we
; store to stack if passing more.
; Function Attrs: norecurse nounwind readonly
-define fp128 @testStruct_03(%struct.With9fp128params* byval nocapture readonly
- align 16 %a) {
+define fp128 @testStruct_03(%struct.With9fp128params* byval nocapture readonly align 16 %a) {
; CHECK-LABEL: testStruct_03:
; CHECK: # %bb.0: # %entry
-; CHECK: lxv v2, 128(r1)
-; CHECK-DAG: std r10, 88(r1)
-; CHECK-DAG: std r9, 80(r1)
-; CHECK-DAG: std r8, 72(r1)
-; CHECK-DAG: std r7, 64(r1)
-; CHECK-DAG: std r6, 56(r1)
-; CHECK-DAG: std r5, 48(r1)
-; CHECK-DAG: std r4, 40(r1)
-; CHECK-DAG: std r3, 32(r1)
+; CHECK-NEXT: lxv v2, 128(r1)
+; CHECK-NEXT: std r3, 32(r1)
+; CHECK-NEXT: std r4, 40(r1)
+; CHECK-NEXT: std r5, 48(r1)
+; CHECK-NEXT: std r6, 56(r1)
+; CHECK-NEXT: std r7, 64(r1)
+; CHECK-NEXT: std r8, 72(r1)
+; CHECK-NEXT: std r9, 80(r1)
+; CHECK-NEXT: std r10, 88(r1)
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testStruct_03:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE: lxv v2, 144(r1)
-; CHECK-BE-DAG: std r10, 104(r1)
-; CHECK-BE-DAG: std r9, 96(r1)
-; CHECK-BE-DAG: std r8, 88(r1)
-; CHECK-BE-DAG: std r7, 80(r1)
-; CHECK-BE-DAG: std r6, 72(r1)
-; CHECK-BE-DAG: std r5, 64(r1)
-; CHECK-BE-DAG: std r4, 56(r1)
-; CHECK-BE-DAG: std r3, 48(r1)
+; CHECK-BE-NEXT: lxv v2, 144(r1)
+; CHECK-BE-NEXT: std r3, 48(r1)
+; CHECK-BE-NEXT: std r4, 56(r1)
+; CHECK-BE-NEXT: std r5, 64(r1)
+; CHECK-BE-NEXT: std r6, 72(r1)
+; CHECK-BE-NEXT: std r7, 80(r1)
+; CHECK-BE-NEXT: std r8, 88(r1)
+; CHECK-BE-NEXT: std r9, 96(r1)
+; CHECK-BE-NEXT: std r10, 104(r1)
; CHECK-BE-NEXT: blr
+
entry:
%a7 = getelementptr inbounds %struct.With9fp128params,
%struct.With9fp128params* %a, i64 0, i32 6
@@ -117,10 +127,12 @@ define fp128 @testStruct_04([8 x fp128] %a.coerce) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmr v2, v5
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testStruct_04:
-; CHECK-BE: vmr v2, v5
-; CHECK-BE-NEXT: blr
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: vmr v2, v5
+; CHECK-BE-NEXT: blr
+
entry:
%a.coerce.fca.3.extract = extractvalue [8 x fp128] %a.coerce, 3
ret fp128 %a.coerce.fca.3.extract
@@ -131,10 +143,11 @@ define fp128 @testHUnion_01([1 x fp128] %a.coerce) {
; CHECK-LABEL: testHUnion_01:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testHUnion_01:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: blr
+; CHECK-BE-NEXT: blr
+
entry:
%a.coerce.fca.0.extract = extractvalue [1 x fp128] %a.coerce, 0
ret fp128 %a.coerce.fca.0.extract
@@ -145,10 +158,11 @@ define fp128 @testHUnion_02([3 x fp128] %a.coerce) {
; CHECK-LABEL: testHUnion_02:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testHUnion_02:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: blr
+; CHECK-BE-NEXT: blr
+
entry:
%a.coerce.fca.0.extract = extractvalue [3 x fp128] %a.coerce, 0
ret fp128 %a.coerce.fca.0.extract
@@ -160,11 +174,12 @@ define fp128 @testHUnion_03([3 x fp128] %a.coerce) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmr v2, v3
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testHUnion_03:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vmr v2, v3
-; CHECK-BE-NEXT: blr
+; CHECK-BE-NEXT: vmr v2, v3
+; CHECK-BE-NEXT: blr
+
entry:
%a.coerce.fca.1.extract = extractvalue [3 x fp128] %a.coerce, 1
ret fp128 %a.coerce.fca.1.extract
@@ -176,11 +191,12 @@ define fp128 @testHUnion_04([3 x fp128] %a.coerce) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmr v2, v4
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testHUnion_04:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vmr v2, v4
-; CHECK-BE-NEXT: blr
+; CHECK-BE-NEXT: vmr v2, v4
+; CHECK-BE-NEXT: blr
+
entry:
%a.coerce.fca.2.extract = extractvalue [3 x fp128] %a.coerce, 2
ret fp128 %a.coerce.fca.2.extract
@@ -197,10 +213,12 @@ define fp128 @testMixedAggregate([3 x i128] %a.coerce) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrdd v2, r8, r7
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testMixedAggregate:
-; CHECK-BE: mtvsrdd v2, r8, r7
-; CHECK-BE-NEXT: blr
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: mtvsrdd v2, r8, r7
+; CHECK-BE-NEXT: blr
+
entry:
%a.coerce.fca.2.extract = extractvalue [3 x i128] %a.coerce, 2
%0 = bitcast i128 %a.coerce.fca.2.extract to fp128
@@ -213,10 +231,12 @@ define fp128 @testMixedAggregate_02([4 x i128] %a.coerce) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrdd v2, r6, r5
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testMixedAggregate_02:
-; CHECK-BE: mtvsrdd v2, r6, r5
-; CHECK-BE-NEXT: blr
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: mtvsrdd v2, r6, r5
+; CHECK-BE-NEXT: blr
+
entry:
%a.coerce.fca.1.extract = extractvalue [4 x i128] %a.coerce, 1
%0 = bitcast i128 %a.coerce.fca.1.extract to fp128
@@ -227,14 +247,25 @@ entry:
define fp128 @testMixedAggregate_03([4 x i128] %sa.coerce) {
; CHECK-LABEL: testMixedAggregate_03:
; CHECK: # %bb.0: # %entry
-; CHECK: mtvsrwa v2, r3
-; CHECK-DAG: xscvsdqp v2, v2
-; CHECK-DAG: mtvsrdd v3, r6, r5
-; CHECK: xsaddqp v2, v3, v2
-; CHECK: mtvsrd v[[REG1:[0-9]+]], r10
-; CHECK: xscvsdqp v[[REG:[0-9]+]], v[[REG1]]
-; CHECK: xsaddqp v2, v2, v[[REG]]
+; CHECK-NEXT: mtvsrwa v2, r3
+; CHECK-NEXT: mtvsrdd v3, r6, r5
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: xsaddqp v2, v3, v2
+; CHECK-NEXT: mtvsrd v3, r10
+; CHECK-NEXT: xscvsdqp v3, v3
+; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr
+;
+; CHECK-BE-LABEL: testMixedAggregate_03:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: mtvsrwa v2, r4
+; CHECK-BE-NEXT: mtvsrdd v3, r6, r5
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: xsaddqp v2, v3, v2
+; CHECK-BE-NEXT: mtvsrd v3, r9
+; CHECK-BE-NEXT: xscvsdqp v3, v3
+; CHECK-BE-NEXT: xsaddqp v2, v2, v3
+; CHECK-BE-NEXT: blr
entry:
%sa.coerce.fca.0.extract = extractvalue [4 x i128] %sa.coerce, 0
%sa.sroa.0.0.extract.trunc = trunc i128 %sa.coerce.fca.0.extract to i32
@@ -255,29 +286,30 @@ entry:
define fp128 @testNestedAggregate(%struct.MixedC* byval nocapture readonly align 16 %a) {
; CHECK-LABEL: testNestedAggregate:
; CHECK: # %bb.0: # %entry
-; CHECK-DAG: std r8, 72(r1)
-; CHECK-DAG: std r7, 64(r1)
-; CHECK: lxv v2, 64(r1)
-; CHECK-DAG: std r10, 88(r1)
-; CHECK-DAG: std r9, 80(r1)
-; CHECK-DAG: std r6, 56(r1)
-; CHECK-DAG: std r5, 48(r1)
-; CHECK-DAG: std r4, 40(r1)
-; CHECK-DAG: std r3, 32(r1)
+; CHECK-NEXT: std r8, 72(r1)
+; CHECK-NEXT: std r7, 64(r1)
+; CHECK-NEXT: lxv v2, 64(r1)
+; CHECK-NEXT: std r3, 32(r1)
+; CHECK-NEXT: std r4, 40(r1)
+; CHECK-NEXT: std r5, 48(r1)
+; CHECK-NEXT: std r6, 56(r1)
+; CHECK-NEXT: std r9, 80(r1)
+; CHECK-NEXT: std r10, 88(r1)
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testNestedAggregate:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-DAG: std r8, 88(r1)
-; CHECK-BE-DAG: std r7, 80(r1)
+; CHECK-BE-NEXT: std r8, 88(r1)
+; CHECK-BE-NEXT: std r7, 80(r1)
; CHECK-BE-NEXT: lxv v2, 80(r1)
-; CHECK-BE-DAG: std r10, 104(r1)
-; CHECK-BE-DAG: std r9, 96(r1)
-; CHECK-BE-DAG: std r6, 72(r1)
-; CHECK-BE-DAG: std r5, 64(r1)
-; CHECK-BE-DAG: std r4, 56(r1)
-; CHECK-BE-DAG: std r3, 48(r1)
+; CHECK-BE-NEXT: std r3, 48(r1)
+; CHECK-BE-NEXT: std r4, 56(r1)
+; CHECK-BE-NEXT: std r5, 64(r1)
+; CHECK-BE-NEXT: std r6, 72(r1)
+; CHECK-BE-NEXT: std r9, 96(r1)
+; CHECK-BE-NEXT: std r10, 104(r1)
; CHECK-BE-NEXT: blr
+
entry:
%c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1
%0 = load fp128, fp128* %c, align 16
@@ -290,10 +322,12 @@ define fp128 @testUnion_01([1 x i128] %a.coerce) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrdd v2, r4, r3
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testUnion_01:
-; CHECK-BE: mtvsrdd v2, r4, r3
-; CHECK-BE-NEXT: blr
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: mtvsrdd v2, r4, r3
+; CHECK-BE-NEXT: blr
+
entry:
%a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0
%0 = bitcast i128 %a.coerce.fca.0.extract to fp128
@@ -306,10 +340,12 @@ define fp128 @testUnion_02([1 x i128] %a.coerce) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrdd v2, r4, r3
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testUnion_02:
-; CHECK-BE: mtvsrdd v2, r4, r3
-; CHECK-BE-NEXT: blr
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: mtvsrdd v2, r4, r3
+; CHECK-BE-NEXT: blr
+
entry:
%a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0
%0 = bitcast i128 %a.coerce.fca.0.extract to fp128
@@ -322,10 +358,12 @@ define fp128 @testUnion_03([4 x i128] %a.coerce) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrdd v2, r8, r7
; CHECK-NEXT: blr
-
+;
; CHECK-BE-LABEL: testUnion_03:
-; CHECK-BE: mtvsrdd v2, r8, r7
-; CHECK-BE-NEXT: blr
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: mtvsrdd v2, r8, r7
+; CHECK-BE-NEXT: blr
+
entry:
%a.coerce.fca.2.extract = extractvalue [4 x i128] %a.coerce, 2
%0 = bitcast i128 %a.coerce.fca.2.extract to fp128
@@ -336,27 +374,51 @@ entry:
define fp128 @sum_float128(i32 signext %count, ...) {
; CHECK-LABEL: sum_float128:
; CHECK: # %bb.0: # %entry
-; CHECK-DAG: std r10, 88(r1)
-; CHECK-DAG: std r9, 80(r1)
-; CHECK-DAG: std r8, 72(r1)
-; CHECK-DAG: std r7, 64(r1)
-; CHECK-DAG: std r6, 56(r1)
-; CHECK-DAG: std r4, 40(r1)
-; CHECK-DAG: cmpwi r3, 1
-; CHECK-DAG: std r5, 48(r1)
-; CHECK-DAG: addis [[REG:r[0-9]+]], r2, .LCPI17_0 at toc@ha
-; CHECK-DAG: addi [[REG1:r[0-9]+]], [[REG]], .LCPI17_0 at toc@l
-; CHECK-DAG: lxvx v2, 0, [[REG1]]
+; CHECK-NEXT: std r4, 40(r1)
+; CHECK-NEXT: addis r4, r2, .LCPI17_0 at toc@ha
+; CHECK-NEXT: cmpwi r3, 1
+; CHECK-NEXT: std r5, 48(r1)
+; CHECK-NEXT: addi r4, r4, .LCPI17_0 at toc@l
+; CHECK-NEXT: std r6, 56(r1)
+; CHECK-NEXT: std r7, 64(r1)
+; CHECK-NEXT: std r8, 72(r1)
+; CHECK-NEXT: lxvx v2, 0, r4
+; CHECK-NEXT: std r9, 80(r1)
+; CHECK-NEXT: std r10, 88(r1)
; CHECK-NEXT: bltlr cr0
; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: addi r3, r1, 40
-; CHECK-NEXT: addi [[REG2:r[0-9]+]], r1, 72
+; CHECK-NEXT: addi r4, r1, 72
; CHECK-NEXT: lxvx v3, 0, r3
-; CHECK-NEXT: std [[REG2]], -8(r1)
+; CHECK-NEXT: std r4, -8(r1)
; CHECK-NEXT: xsaddqp v2, v3, v2
; CHECK-NEXT: lxv v3, 16(r3)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr
+;
+; CHECK-BE-LABEL: sum_float128:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: std r4, 56(r1)
+; CHECK-BE-NEXT: addis r4, r2, .LCPI17_0 at toc@ha
+; CHECK-BE-NEXT: cmpwi r3, 1
+; CHECK-BE-NEXT: std r5, 64(r1)
+; CHECK-BE-NEXT: addi r4, r4, .LCPI17_0 at toc@l
+; CHECK-BE-NEXT: std r6, 72(r1)
+; CHECK-BE-NEXT: std r7, 80(r1)
+; CHECK-BE-NEXT: std r8, 88(r1)
+; CHECK-BE-NEXT: lxvx v2, 0, r4
+; CHECK-BE-NEXT: std r9, 96(r1)
+; CHECK-BE-NEXT: std r10, 104(r1)
+; CHECK-BE-NEXT: bltlr cr0
+; CHECK-BE-NEXT: # %bb.1: # %if.end
+; CHECK-BE-NEXT: addi r3, r1, 56
+; CHECK-BE-NEXT: addi r4, r1, 88
+; CHECK-BE-NEXT: lxvx v3, 0, r3
+; CHECK-BE-NEXT: std r4, -8(r1)
+; CHECK-BE-NEXT: xsaddqp v2, v3, v2
+; CHECK-BE-NEXT: lxv v3, 16(r3)
+; CHECK-BE-NEXT: xsaddqp v2, v2, v3
+; CHECK-BE-NEXT: blr
entry:
%ap = alloca i8*, align 8
%0 = bitcast i8** %ap to i8*
diff --git a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll
index 028a9855a67b..f4bdd6008906 100644
--- a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
@@ -5,9 +6,9 @@
define fp128 @loadConstant() {
; CHECK-LABEL: loadConstant:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r[[REG0:[0-9]+]], r2, .LCPI0_0 at toc@ha
-; CHECK-NEXT: addi r[[REG0]], r[[REG0]], .LCPI0_0 at toc@l
-; CHECK-NEXT: lxvx v2, 0, r[[REG0]]
+; CHECK-NEXT: addis r3, r2, .LCPI0_0 at toc@ha
+; CHECK-NEXT: addi r3, r3, .LCPI0_0 at toc@l
+; CHECK-NEXT: lxvx v2, 0, r3
; CHECK-NEXT: blr
entry:
ret fp128 0xL00000000000000004001400000000000
@@ -18,10 +19,10 @@ define fp128 @loadConstant2(fp128 %a, fp128 %b) {
; CHECK-LABEL: loadConstant2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xsaddqp v2, v2, v3
-; CHECK-NEXT: addis r[[REG0:[0-9]+]], r2, .LCPI1_0 at toc@ha
-; CHECK-NEXT: addi r[[REG0]], r[[REG0]], .LCPI1_0 at toc@l
-; CHECK-NEXT: lxvx v[[REG1:[0-9]+]], 0, r[[REG0]]
-; CHECK-NEXT: xsaddqp v2, v2, v[[REG1]]
+; CHECK-NEXT: addis r3, r2, .LCPI1_0 at toc@ha
+; CHECK-NEXT: addi r3, r3, .LCPI1_0 at toc@l
+; CHECK-NEXT: lxvx v3, 0, r3
+; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr
entry:
%add = fadd fp128 %a, %b
@@ -62,8 +63,8 @@ define fp128 @fp128Array(fp128* nocapture readonly %farray,
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sldi r4, r4, 4
; CHECK-NEXT: lxv v2, 0(r3)
-; CHECK-NEXT: add [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: lxv v3, -16([[REG]])
+; CHECK-NEXT: add r3, r3, r4
+; CHECK-NEXT: lxv v3, -16(r3)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr
i32 signext %loopcnt, fp128* nocapture readnone %sum) {
@@ -84,7 +85,7 @@ define fp128 @maxVecParam(fp128 %p1, fp128 %p2, fp128 %p3, fp128 %p4, fp128 %p5,
; CHECK-LABEL: maxVecParam:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xsaddqp v2, v2, v3
-; CHECK-NEXT: lxv v[[REG0:[0-9]+]], 224(r1)
+; CHECK-NEXT: lxv v0, 224(r1)
; CHECK-NEXT: xsaddqp v2, v2, v4
; CHECK-NEXT: xsaddqp v2, v2, v5
; CHECK-NEXT: xsaddqp v2, v2, v6
@@ -95,7 +96,7 @@ define fp128 @maxVecParam(fp128 %p1, fp128 %p2, fp128 %p3, fp128 %p4, fp128 %p5,
; CHECK-NEXT: xsaddqp v2, v2, v11
; CHECK-NEXT: xsaddqp v2, v2, v12
; CHECK-NEXT: xsaddqp v2, v2, v13
-; CHECK-NEXT: xssubqp v2, v2, v[[REG0]]
+; CHECK-NEXT: xssubqp v2, v2, v0
; CHECK-NEXT: blr
fp128 %p6, fp128 %p7, fp128 %p8, fp128 %p9, fp128 %p10,
fp128 %p11, fp128 %p12, fp128 %p13) {
@@ -120,10 +121,10 @@ entry:
define fp128 @mixParam_01(fp128 %a, i32 signext %i, fp128 %b) {
; CHECK-LABEL: mixParam_01:
; CHECK: # %bb.0: # %entry
-; CHECK-DAG: mtvsrwa [[REG1:v[0-9]+]], r5
-; CHECK-DAG: xsaddqp v2, v2, v3
-; CHECK-NEXT: xscvsdqp v[[REG0:[0-9]+]], [[REG1]]
-; CHECK-NEXT: xsaddqp v2, v2, v[[REG0]]
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: mtvsrwa v3, r5
+; CHECK-NEXT: xscvsdqp v3, v3
+; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr
entry:
%add = fadd fp128 %a, %b
@@ -135,10 +136,10 @@ entry:
define fastcc fp128 @mixParam_01f(fp128 %a, i32 signext %i, fp128 %b) {
; CHECK-LABEL: mixParam_01f:
; CHECK: # %bb.0: # %entry
-; CHECK-DAG: mtvsrwa v[[REG0:[0-9]+]], r3
-; CHECK-DAG: xsaddqp v2, v2, v3
-; CHECK-NEXT: xscvsdqp v[[REG1:[0-9]+]], v[[REG0]]
-; CHECK-NEXT: xsaddqp v2, v2, v[[REG1]]
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: mtvsrwa v3, r3
+; CHECK-NEXT: xscvsdqp v3, v3
+; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr
entry:
%add = fadd fp128 %a, %b
@@ -151,17 +152,17 @@ entry:
define fp128 @mixParam_02(fp128 %p1, double %p2, i64* nocapture %p3,
; CHECK-LABEL: mixParam_02:
; CHECK: # %bb.0: # %entry
-; CHECK: lwz r3, 96(r1)
-; CHECK: add r4, r7, r9
-; CHECK: xscpsgndp v[[REG0:[0-9]+]], f1, f1
-; CHECK: add r4, r4, r10
-; CHECK: xscvdpqp v[[REG0]], v[[REG0]]
-; CHECK: add r3, r4, r3
-; CHECK: clrldi r3, r3, 32
-; CHECK: std r3, 0(r6)
-; CHECK: lxv v[[REG1:[0-9]+]], 0(r8)
-; CHECK: xsaddqp v2, v[[REG1]], v2
-; CHECK: xsaddqp v2, v2, v3
+; CHECK-NEXT: lwz r3, 96(r1)
+; CHECK-NEXT: add r4, r7, r9
+; CHECK-NEXT: xscpsgndp v3, f1, f1
+; CHECK-NEXT: add r4, r4, r10
+; CHECK-NEXT: xscvdpqp v3, v3
+; CHECK-NEXT: add r3, r4, r3
+; CHECK-NEXT: clrldi r3, r3, 32
+; CHECK-NEXT: std r3, 0(r6)
+; CHECK-NEXT: lxv v4, 0(r8)
+; CHECK-NEXT: xsaddqp v2, v4, v2
+; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr
i16 signext %p4, fp128* nocapture readonly %p5,
i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) {
@@ -185,15 +186,15 @@ define fastcc fp128 @mixParam_02f(fp128 %p1, double %p2, i64* nocapture %p3,
; CHECK-LABEL: mixParam_02f:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: add r4, r4, r6
-; CHECK-NEXT: xscpsgndp v[[REG0:[0-9]+]], f1, f1
+; CHECK-NEXT: xscpsgndp v3, f1, f1
; CHECK-NEXT: add r4, r4, r7
-; CHECK-NEXT: xscvdpqp v[[REG0]], v[[REG0]]
+; CHECK-NEXT: xscvdpqp v3, v3
; CHECK-NEXT: add r4, r4, r8
; CHECK-NEXT: clrldi r4, r4, 32
-; CHECK-DAG: std r4, 0(r3)
-; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r5)
-; CHECK-NEXT: xsaddqp v2, v[[REG1]], v2
-; CHECK-NEXT: xsaddqp v2, v2, v[[REG0]]
+; CHECK-NEXT: std r4, 0(r3)
+; CHECK-NEXT: lxv v4, 0(r5)
+; CHECK-NEXT: xsaddqp v2, v4, v2
+; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr
i16 signext %p4, fp128* nocapture readonly %p5,
i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) {
@@ -217,13 +218,13 @@ entry:
define void @mixParam_03(fp128 %f1, double* nocapture %d1, <4 x i32> %vec1,
; CHECK-LABEL: mixParam_03:
; CHECK: # %bb.0: # %entry
-; CHECK-DAG: ld r3, 104(r1)
-; CHECK-DAG: stxv v2, 0(r9)
-; CHECK: stxvx v3, 0, r3
-; CHECK: mtvsrwa v[[REG2:[0-9]+]], r10
-; CHECK-DAG: xscvsdqp v[[REG1:[0-9]+]], v[[REG2]]
-; CHECK-DAG: lxv v2, 0(r9)
-; CHECK-NEXT: xsaddqp v2, v2, v[[REG1]]
+; CHECK-NEXT: ld r3, 104(r1)
+; CHECK-NEXT: stxv v2, 0(r9)
+; CHECK-NEXT: stxvx v3, 0, r3
+; CHECK-NEXT: mtvsrwa v3, r10
+; CHECK-NEXT: lxv v2, 0(r9)
+; CHECK-NEXT: xscvsdqp v3, v3
+; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpdp v2, v2
; CHECK-NEXT: stxsd v2, 0(r5)
; CHECK-NEXT: blr
@@ -244,13 +245,13 @@ entry:
define fastcc void @mixParam_03f(fp128 %f1, double* nocapture %d1, <4 x i32> %vec1,
; CHECK-LABEL: mixParam_03f:
; CHECK: # %bb.0: # %entry
-; CHECK-DAG: mtvsrwa v[[REG0:[0-9]+]], r5
-; CHECK-DAG: stxv v[[REG1:[0-9]+]], 0(r4)
-; CHECK-DAG: stxv v[[REG2:[0-9]+]], 0(r7)
-; CHECK-DAG: lxv v[[REG1]], 0(r4)
-; CHECK-NEXT: xscvsdqp v[[REG3:[0-9]+]], v[[REG0]]
-; CHECK-NEXT: xsaddqp v[[REG4:[0-9]+]], v[[REG1]], v[[REG3]]
-; CHECK-NEXT: xscvqpdp v2, v[[REG4]]
+; CHECK-NEXT: stxv v2, 0(r4)
+; CHECK-NEXT: stxv v3, 0(r7)
+; CHECK-NEXT: lxv v2, 0(r4)
+; CHECK-NEXT: mtvsrwa v3, r5
+; CHECK-NEXT: xscvsdqp v3, v3
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: xscvqpdp v2, v2
; CHECK-NEXT: stxsd v2, 0(r3)
; CHECK-NEXT: blr
fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1,
diff --git a/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll b/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll
index b3ccc4e6646f..666303406a7d 100644
--- a/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll
+++ b/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64"
@@ -6,6 +7,15 @@ target triple = "powerpc64le-unknown-linux-gnu"
@g = common global ppc_fp128 0xM00000000000000000000000000000000, align 16
define void @callee(ppc_fp128 %x) {
+; CHECK-LABEL: callee:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis 3, 2, .LC0 at toc@ha
+; CHECK-NEXT: stfd 2, -8(1)
+; CHECK-NEXT: stfd 1, -16(1)
+; CHECK-NEXT: ld 3, .LC0 at toc@l(3)
+; CHECK-NEXT: stfd 2, 8(3)
+; CHECK-NEXT: stfd 1, 0(3)
+; CHECK-NEXT: blr
entry:
%x.addr = alloca ppc_fp128, align 16
store ppc_fp128 %x, ppc_fp128* %x.addr, align 16
@@ -13,133 +23,194 @@ entry:
store ppc_fp128 %0, ppc_fp128* @g, align 16
ret void
}
-; CHECK-LABEL: @callee
-; CHECK: ld [[REG:[0-9]+]], .LC
-; CHECK: stfd 2, 8([[REG]])
-; CHECK: stfd 1, 0([[REG]])
-; CHECK: blr
define void @caller() {
+; CHECK-LABEL: caller:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: std 0, 16(1)
+; CHECK-NEXT: stdu 1, -32(1)
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: .cfi_offset lr, 16
+; CHECK-NEXT: addis 3, 2, .LC0 at toc@ha
+; CHECK-NEXT: ld 3, .LC0 at toc@l(3)
+; CHECK-NEXT: lfd 2, 8(3)
+; CHECK-NEXT: lfd 1, 0(3)
+; CHECK-NEXT: bl test
+; CHECK-NEXT: nop
+; CHECK-NEXT: addi 1, 1, 32
+; CHECK-NEXT: ld 0, 16(1)
+; CHECK-NEXT: mtlr 0
+; CHECK-NEXT: blr
entry:
%0 = load ppc_fp128, ppc_fp128* @g, align 16
call void @test(ppc_fp128 %0)
ret void
}
-; CHECK-LABEL: @caller
-; CHECK: ld [[REG:[0-9]+]], .LC
-; CHECK: lfd 2, 8([[REG]])
-; CHECK: lfd 1, 0([[REG]])
-; CHECK: bl test
declare void @test(ppc_fp128)
define void @caller_const() {
+; CHECK-LABEL: caller_const:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: std 0, 16(1)
+; CHECK-NEXT: stdu 1, -32(1)
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: .cfi_offset lr, 16
+; CHECK-NEXT: addis 3, 2, .LCPI2_0 at toc@ha
+; CHECK-NEXT: addis 4, 2, .LCPI2_1 at toc@ha
+; CHECK-NEXT: lfs 1, .LCPI2_0 at toc@l(3)
+; CHECK-NEXT: lfs 2, .LCPI2_1 at toc@l(4)
+; CHECK-NEXT: bl test
+; CHECK-NEXT: nop
+; CHECK-NEXT: addi 1, 1, 32
+; CHECK-NEXT: ld 0, 16(1)
+; CHECK-NEXT: mtlr 0
+; CHECK-NEXT: blr
entry:
call void @test(ppc_fp128 0xM3FF00000000000000000000000000000)
ret void
}
-; CHECK: .LCPI[[LC:[0-9]+]]_0:
-; CHECK: .long 0x3f800000
-; CHECK: .LCPI[[LC]]_1:
-; CHECK: .long 0
-; CHECK-LABEL: @caller_const
-; CHECK: addis [[REG0:[0-9]+]], 2, .LCPI[[LC]]_0 at toc@ha
-; CHECK: addis [[REG1:[0-9]+]], 2, .LCPI[[LC]]_1 at toc@ha
-; CHECK: lfs 1, .LCPI[[LC]]_0 at toc@l([[REG0]])
-; CHECK: lfs 2, .LCPI[[LC]]_1 at toc@l([[REG1]])
-; CHECK: bl test
define ppc_fp128 @result() {
+; CHECK-LABEL: result:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis 3, 2, .LC0 at toc@ha
+; CHECK-NEXT: ld 3, .LC0 at toc@l(3)
+; CHECK-NEXT: lfd 1, 0(3)
+; CHECK-NEXT: lfd 2, 8(3)
+; CHECK-NEXT: blr
entry:
%0 = load ppc_fp128, ppc_fp128* @g, align 16
ret ppc_fp128 %0
}
-; CHECK-LABEL: @result
-; CHECK: ld [[REG:[0-9]+]], .LC
-; CHECK: lfd 1, 0([[REG]])
-; CHECK: lfd 2, 8([[REG]])
-; CHECK: blr
define void @use_result() {
+; CHECK-LABEL: use_result:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: std 0, 16(1)
+; CHECK-NEXT: stdu 1, -32(1)
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: .cfi_offset lr, 16
+; CHECK-NEXT: bl test_result
+; CHECK-NEXT: nop
+; CHECK-NEXT: addis 3, 2, .LC0 at toc@ha
+; CHECK-NEXT: ld 3, .LC0 at toc@l(3)
+; CHECK-NEXT: stfd 2, 8(3)
+; CHECK-NEXT: stfd 1, 0(3)
+; CHECK-NEXT: addi 1, 1, 32
+; CHECK-NEXT: ld 0, 16(1)
+; CHECK-NEXT: mtlr 0
+; CHECK-NEXT: blr
entry:
%call = tail call ppc_fp128 @test_result() #3
store ppc_fp128 %call, ppc_fp128* @g, align 16
ret void
}
-; CHECK-LABEL: @use_result
-; CHECK: bl test_result
-; CHECK: ld [[REG:[0-9]+]], .LC
-; CHECK: stfd 2, 8([[REG]])
-; CHECK: stfd 1, 0([[REG]])
-; CHECK: blr
declare ppc_fp128 @test_result()
define void @caller_result() {
+; CHECK-LABEL: caller_result:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: std 0, 16(1)
+; CHECK-NEXT: stdu 1, -32(1)
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: .cfi_offset lr, 16
+; CHECK-NEXT: bl test_result
+; CHECK-NEXT: nop
+; CHECK-NEXT: bl test
+; CHECK-NEXT: nop
+; CHECK-NEXT: addi 1, 1, 32
+; CHECK-NEXT: ld 0, 16(1)
+; CHECK-NEXT: mtlr 0
+; CHECK-NEXT: blr
entry:
%call = tail call ppc_fp128 @test_result()
tail call void @test(ppc_fp128 %call)
ret void
}
-; CHECK-LABEL: @caller_result
-; CHECK: bl test_result
-; CHECK-NEXT: nop
-; CHECK-NEXT: bl test
-; CHECK-NEXT: nop
define i128 @convert_from(ppc_fp128 %x) {
+; CHECK-LABEL: convert_from:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stfd 1, -16(1)
+; CHECK-NEXT: stfd 2, -8(1)
+; CHECK-NEXT: ld 3, -16(1)
+; CHECK-NEXT: ld 4, -8(1)
+; CHECK-NEXT: blr
entry:
%0 = bitcast ppc_fp128 %x to i128
ret i128 %0
}
-; CHECK-LABEL: @convert_from
-; CHECK: stfd 1, [[OFF1:.*]](1)
-; CHECK: stfd 2, [[OFF2:.*]](1)
-; CHECK: ld 3, [[OFF1]](1)
-; CHECK: ld 4, [[OFF2]](1)
-; CHECK: blr
define ppc_fp128 @convert_to(i128 %x) {
+; CHECK-LABEL: convert_to:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: std 3, -16(1)
+; CHECK-NEXT: std 4, -8(1)
+; CHECK-NEXT: lfd 1, -16(1)
+; CHECK-NEXT: lfd 2, -8(1)
+; CHECK-NEXT: blr
entry:
%0 = bitcast i128 %x to ppc_fp128
ret ppc_fp128 %0
}
-; CHECK-LABEL: convert_to:
-; CHECK-DAG: std 3, [[OFF1:.*]](1)
-; CHECK-DAG: std 4, [[OFF2:.*]](1)
-; CHECK: lfd 1, [[OFF1]](1)
-; CHECK: lfd 2, [[OFF2]](1)
-; CHECK: blr
define ppc_fp128 @convert_to2(i128 %x) {
+; CHECK-LABEL: convert_to2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: rotldi 5, 3, 1
+; CHECK-NEXT: sldi 3, 3, 1
+; CHECK-NEXT: rldimi 5, 4, 1, 0
+; CHECK-NEXT: std 3, -16(1)
+; CHECK-NEXT: std 5, -8(1)
+; CHECK-NEXT: lfd 1, -16(1)
+; CHECK-NEXT: lfd 2, -8(1)
+; CHECK-NEXT: blr
entry:
%shl = shl i128 %x, 1
%0 = bitcast i128 %shl to ppc_fp128
ret ppc_fp128 %0
}
-; CHECK-LABEL: convert_to2:
-; CHECK: std 3, [[OFF1:.*]](1)
-; CHECK: std 5, [[OFF2:.*]](1)
-; CHECK: lfd 1, [[OFF1]](1)
-; CHECK: lfd 2, [[OFF2]](1)
-; CHECK: blr
define double @convert_vector(<4 x i32> %x) {
+; CHECK-LABEL: convert_vector:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi 3, 1, -16
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: lfd 1, -16(1)
+; CHECK-NEXT: blr
entry:
%cast = bitcast <4 x i32> %x to ppc_fp128
%conv = fptrunc ppc_fp128 %cast to double
ret double %conv
}
-; CHECK-LABEL: @convert_vector
-; CHECK: addi [[REG:[0-9]+]], 1, [[OFF:.*]]
-; CHECK: stvx 2, 0, [[REG]]
-; CHECK: lfd 1, [[OFF]](1)
-; CHECK: blr
declare void @llvm.va_start(i8*)
define double @vararg(i32 %a, ...) {
+; CHECK-LABEL: vararg:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi 3, 1, 55
+; CHECK-NEXT: std 4, 40(1)
+; CHECK-NEXT: rldicr 3, 3, 0, 59
+; CHECK-NEXT: std 5, 48(1)
+; CHECK-NEXT: ori 4, 3, 8
+; CHECK-NEXT: std 6, 56(1)
+; CHECK-NEXT: std 7, 64(1)
+; CHECK-NEXT: std 8, 72(1)
+; CHECK-NEXT: std 9, 80(1)
+; CHECK-NEXT: std 10, 88(1)
+; CHECK-NEXT: std 4, -8(1)
+; CHECK-NEXT: lfd 1, 0(3)
+; CHECK-NEXT: addi 3, 3, 16
+; CHECK-NEXT: std 3, -8(1)
+; CHECK-NEXT: blr
entry:
%va = alloca i8*, align 8
%va1 = bitcast i8** %va to i8*
@@ -148,7 +219,4 @@ entry:
%conv = fptrunc ppc_fp128 %arg to double
ret double %conv
}
-; CHECK-LABEL: @vararg
-; CHECK: lfd 1, 0({{[0-9]+}})
-; CHECK: blr
diff --git a/llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll b/llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
index 67262f472b32..4ee8ca335335 100644
--- a/llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
@@ -9,6 +10,20 @@
; Function Attrs: norecurse nounwind readonly
define <4 x i32> @s2v_test1(i32* nocapture readonly %int32, <4 x i32> %vec) {
+; P9LE-LABEL: s2v_test1:
+; P9LE: # %bb.0: # %entry
+; P9LE-NEXT: lwz r3, 0(r3)
+; P9LE-NEXT: mtfprwz f0, r3
+; P9LE-NEXT: xxinsertw v2, vs0, 12
+; P9LE-NEXT: blr
+;
+; P9BE-LABEL: s2v_test1:
+; P9BE: # %bb.0: # %entry
+; P9BE-NEXT: lwz r3, 0(r3)
+; P9BE-NEXT: mtfprwz f0, r3
+; P9BE-NEXT: xxinsertw v2, vs0, 0
+; P9BE-NEXT: blr
+;
; P8LE-LABEL: s2v_test1:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r4, r2, .LCPI0_0 at toc@ha
@@ -17,13 +32,13 @@ define <4 x i32> @s2v_test1(i32* nocapture readonly %int32, <4 x i32> %vec) {
; P8LE-NEXT: lvx v3, 0, r4
; P8LE-NEXT: vperm v2, v2, v4, v3
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test1:
; P8BE: # %bb.0: # %entry
-; P8BE: lfiwzx f0, 0, r3
+; P8BE-NEXT: lfiwzx f0, 0, r3
; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
-; P8BE: xxsldwi vs0, v2, vs0, 1
-; P8BE: xxsldwi v2, vs0, vs0, 3
+; P8BE-NEXT: xxsldwi vs0, v2, vs0, 1
+; P8BE-NEXT: xxsldwi v2, vs0, vs0, 3
; P8BE-NEXT: blr
entry:
%0 = load i32, i32* %int32, align 4
@@ -33,6 +48,20 @@ entry:
; Function Attrs: norecurse nounwind readonly
define <4 x i32> @s2v_test2(i32* nocapture readonly %int32, <4 x i32> %vec) {
+; P9LE-LABEL: s2v_test2:
+; P9LE: # %bb.0: # %entry
+; P9LE-NEXT: lwz r3, 4(r3)
+; P9LE-NEXT: mtfprwz f0, r3
+; P9LE-NEXT: xxinsertw v2, vs0, 12
+; P9LE-NEXT: blr
+;
+; P9BE-LABEL: s2v_test2:
+; P9BE: # %bb.0: # %entry
+; P9BE-NEXT: lwz r3, 4(r3)
+; P9BE-NEXT: mtfprwz f0, r3
+; P9BE-NEXT: xxinsertw v2, vs0, 0
+; P9BE-NEXT: blr
+;
; P8LE-LABEL: s2v_test2:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r4, r2, .LCPI1_0 at toc@ha
@@ -42,14 +71,14 @@ define <4 x i32> @s2v_test2(i32* nocapture readonly %int32, <4 x i32> %vec) {
; P8LE-NEXT: lvx v3, 0, r4
; P8LE-NEXT: vperm v2, v2, v4, v3
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test2:
; P8BE: # %bb.0: # %entry
-; P8BE: addi r3, r3, 4
-; P8BE: lfiwzx f0, 0, r3
+; P8BE-NEXT: addi r3, r3, 4
+; P8BE-NEXT: lfiwzx f0, 0, r3
; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
-; P8BE: xxsldwi vs0, v2, vs0, 1
-; P8BE: xxsldwi v2, vs0, vs0, 3
+; P8BE-NEXT: xxsldwi vs0, v2, vs0, 1
+; P8BE-NEXT: xxsldwi v2, vs0, vs0, 3
; P8BE-NEXT: blr
entry:
%arrayidx = getelementptr inbounds i32, i32* %int32, i64 1
@@ -60,6 +89,22 @@ entry:
; Function Attrs: norecurse nounwind readonly
define <4 x i32> @s2v_test3(i32* nocapture readonly %int32, <4 x i32> %vec, i32 signext %Idx) {
+; P9LE-LABEL: s2v_test3:
+; P9LE: # %bb.0: # %entry
+; P9LE-NEXT: sldi r4, r7, 2
+; P9LE-NEXT: lwzx r3, r3, r4
+; P9LE-NEXT: mtfprwz f0, r3
+; P9LE-NEXT: xxinsertw v2, vs0, 12
+; P9LE-NEXT: blr
+;
+; P9BE-LABEL: s2v_test3:
+; P9BE: # %bb.0: # %entry
+; P9BE-NEXT: sldi r4, r7, 2
+; P9BE-NEXT: lwzx r3, r3, r4
+; P9BE-NEXT: mtfprwz f0, r3
+; P9BE-NEXT: xxinsertw v2, vs0, 0
+; P9BE-NEXT: blr
+;
; P8LE-LABEL: s2v_test3:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r4, r2, .LCPI2_0 at toc@ha
@@ -69,14 +114,14 @@ define <4 x i32> @s2v_test3(i32* nocapture readonly %int32, <4 x i32> %vec, i32
; P8LE-NEXT: lvx v4, 0, r4
; P8LE-NEXT: vperm v2, v2, v3, v4
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test3:
; P8BE: # %bb.0: # %entry
-; P8BE: sldi r4, r7, 2
-; P8BE: lfiwzx f0, r3, r4
+; P8BE-NEXT: sldi r4, r7, 2
+; P8BE-NEXT: lfiwzx f0, r3, r4
; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
-; P8BE: xxsldwi vs0, v2, vs0, 1
-; P8BE: xxsldwi v2, vs0, vs0, 3
+; P8BE-NEXT: xxsldwi vs0, v2, vs0, 1
+; P8BE-NEXT: xxsldwi v2, vs0, vs0, 3
; P8BE-NEXT: blr
entry:
%idxprom = sext i32 %Idx to i64
@@ -88,6 +133,20 @@ entry:
; Function Attrs: norecurse nounwind readonly
define <4 x i32> @s2v_test4(i32* nocapture readonly %int32, <4 x i32> %vec) {
+; P9LE-LABEL: s2v_test4:
+; P9LE: # %bb.0: # %entry
+; P9LE-NEXT: lwz r3, 4(r3)
+; P9LE-NEXT: mtfprwz f0, r3
+; P9LE-NEXT: xxinsertw v2, vs0, 12
+; P9LE-NEXT: blr
+;
+; P9BE-LABEL: s2v_test4:
+; P9BE: # %bb.0: # %entry
+; P9BE-NEXT: lwz r3, 4(r3)
+; P9BE-NEXT: mtfprwz f0, r3
+; P9BE-NEXT: xxinsertw v2, vs0, 0
+; P9BE-NEXT: blr
+;
; P8LE-LABEL: s2v_test4:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r4, r2, .LCPI3_0 at toc@ha
@@ -97,14 +156,14 @@ define <4 x i32> @s2v_test4(i32* nocapture readonly %int32, <4 x i32> %vec) {
; P8LE-NEXT: lvx v3, 0, r4
; P8LE-NEXT: vperm v2, v2, v4, v3
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test4:
; P8BE: # %bb.0: # %entry
-; P8BE: addi r3, r3, 4
-; P8BE: lfiwzx f0, 0, r3
+; P8BE-NEXT: addi r3, r3, 4
+; P8BE-NEXT: lfiwzx f0, 0, r3
; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
-; P8BE: xxsldwi vs0, v2, vs0, 1
-; P8BE: xxsldwi v2, vs0, vs0, 3
+; P8BE-NEXT: xxsldwi vs0, v2, vs0, 1
+; P8BE-NEXT: xxsldwi v2, vs0, vs0, 3
; P8BE-NEXT: blr
entry:
%arrayidx = getelementptr inbounds i32, i32* %int32, i64 1
@@ -115,6 +174,20 @@ entry:
; Function Attrs: norecurse nounwind readonly
define <4 x i32> @s2v_test5(<4 x i32> %vec, i32* nocapture readonly %ptr1) {
+; P9LE-LABEL: s2v_test5:
+; P9LE: # %bb.0: # %entry
+; P9LE-NEXT: lwz r3, 0(r5)
+; P9LE-NEXT: mtfprwz f0, r3
+; P9LE-NEXT: xxinsertw v2, vs0, 12
+; P9LE-NEXT: blr
+;
+; P9BE-LABEL: s2v_test5:
+; P9BE: # %bb.0: # %entry
+; P9BE-NEXT: lwz r3, 0(r5)
+; P9BE-NEXT: mtfprwz f0, r3
+; P9BE-NEXT: xxinsertw v2, vs0, 0
+; P9BE-NEXT: blr
+;
; P8LE-LABEL: s2v_test5:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r3, r2, .LCPI4_0 at toc@ha
@@ -123,13 +196,13 @@ define <4 x i32> @s2v_test5(<4 x i32> %vec, i32* nocapture readonly %ptr1) {
; P8LE-NEXT: lvx v3, 0, r3
; P8LE-NEXT: vperm v2, v2, v4, v3
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test5:
; P8BE: # %bb.0: # %entry
-; P8BE: lfiwzx f0, 0, r5
+; P8BE-NEXT: lfiwzx f0, 0, r5
; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
-; P8BE: xxsldwi vs0, v2, vs0, 1
-; P8BE: xxsldwi v2, vs0, vs0, 3
+; P8BE-NEXT: xxsldwi vs0, v2, vs0, 1
+; P8BE-NEXT: xxsldwi v2, vs0, vs0, 3
; P8BE-NEXT: blr
entry:
%0 = load i32, i32* %ptr1, align 4
@@ -139,6 +212,22 @@ entry:
; Function Attrs: norecurse nounwind readonly
define <4 x float> @s2v_test_f1(float* nocapture readonly %f64, <4 x float> %vec) {
+; P9LE-LABEL: s2v_test_f1:
+; P9LE: # %bb.0: # %entry
+; P9LE-NEXT: lfs f0, 0(r3)
+; P9LE-NEXT: xscvdpspn vs0, f0
+; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 3
+; P9LE-NEXT: xxinsertw v2, vs0, 12
+; P9LE-NEXT: blr
+;
+; P9BE-LABEL: s2v_test_f1:
+; P9BE: # %bb.0: # %entry
+; P9BE-NEXT: lfs f0, 0(r3)
+; P9BE-NEXT: xscvdpspn vs0, f0
+; P9BE-NEXT: xxsldwi vs0, vs0, vs0, 3
+; P9BE-NEXT: xxinsertw v2, vs0, 0
+; P9BE-NEXT: blr
+;
; P8LE-LABEL: s2v_test_f1:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r4, r2, .LCPI5_0 at toc@ha
@@ -147,13 +236,13 @@ define <4 x float> @s2v_test_f1(float* nocapture readonly %f64, <4 x float> %vec
; P8LE-NEXT: lvx v3, 0, r4
; P8LE-NEXT: vperm v2, v2, v4, v3
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test_f1:
; P8BE: # %bb.0: # %entry
-; P8BE: lfiwzx f0, 0, r3
+; P8BE-NEXT: lfiwzx f0, 0, r3
; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
-; P8BE: xxsldwi vs0, v2, vs0, 1
-; P8BE: xxsldwi v2, vs0, vs0, 3
+; P8BE-NEXT: xxsldwi vs0, v2, vs0, 1
+; P8BE-NEXT: xxsldwi v2, vs0, vs0, 3
; P8BE-NEXT: blr
entry:
%0 = load float, float* %f64, align 4
@@ -170,16 +259,16 @@ define <2 x float> @s2v_test_f2(float* nocapture readonly %f64, <2 x float> %vec
; P9LE-NEXT: lxsiwzx v3, 0, r3
; P9LE-NEXT: vmrghw v2, v2, v3
; P9LE-NEXT: blr
-
+;
; P9BE-LABEL: s2v_test_f2:
; P9BE: # %bb.0: # %entry
-; P9BE: addi r3, r3, 4
-; P9BE-DAG: xxspltw v2, v2, 1
-; P9BE-DAG: lfiwzx f0, 0, r3
-; P9BE-NEXT: xxsldwi v3, f0, f0, 1
-; P9BE: vmrghw v2, v3, v2
-; P9BE-NEXT: blr
-
+; P9BE-NEXT: addi r3, r3, 4
+; P9BE-NEXT: xxspltw v2, v2, 1
+; P9BE-NEXT: lfiwzx f0, 0, r3
+; P9BE-NEXT: xxsldwi v3, f0, f0, 1
+; P9BE-NEXT: vmrghw v2, v3, v2
+; P9BE-NEXT: blr
+;
; P8LE-LABEL: s2v_test_f2:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: vmrglw v2, v2, v2
@@ -187,7 +276,7 @@ define <2 x float> @s2v_test_f2(float* nocapture readonly %f64, <2 x float> %vec
; P8LE-NEXT: lxsiwzx v3, 0, r3
; P8LE-NEXT: vmrghw v2, v2, v3
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test_f2:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addi r3, r3, 4
@@ -212,16 +301,16 @@ define <2 x float> @s2v_test_f3(float* nocapture readonly %f64, <2 x float> %vec
; P9LE-NEXT: lxsiwzx v3, r3, r4
; P9LE-NEXT: vmrghw v2, v2, v3
; P9LE-NEXT: blr
-
+;
; P9BE-LABEL: s2v_test_f3:
; P9BE: # %bb.0: # %entry
-; P9BE: sldi r4, r7, 2
-; P9BE-DAG: lfiwzx f0, r3, r4
-; P9BE-DAG: xxspltw v2, v2, 1
-; P9BE: xxsldwi v3, f0, f0, 1
-; P9BE: vmrghw v2, v3, v2
+; P9BE-NEXT: sldi r4, r7, 2
+; P9BE-NEXT: xxspltw v2, v2, 1
+; P9BE-NEXT: lfiwzx f0, r3, r4
+; P9BE-NEXT: xxsldwi v3, f0, f0, 1
+; P9BE-NEXT: vmrghw v2, v3, v2
; P9BE-NEXT: blr
-
+;
; P8LE-LABEL: s2v_test_f3:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: vmrglw v2, v2, v2
@@ -229,7 +318,7 @@ define <2 x float> @s2v_test_f3(float* nocapture readonly %f64, <2 x float> %vec
; P8LE-NEXT: lxsiwzx v3, r3, r4
; P8LE-NEXT: vmrghw v2, v2, v3
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test_f3:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: sldi r4, r7, 2
@@ -255,16 +344,16 @@ define <2 x float> @s2v_test_f4(float* nocapture readonly %f64, <2 x float> %vec
; P9LE-NEXT: lxsiwzx v3, 0, r3
; P9LE-NEXT: vmrghw v2, v2, v3
; P9LE-NEXT: blr
-
+;
; P9BE-LABEL: s2v_test_f4:
; P9BE: # %bb.0: # %entry
-; P9BE: addi r3, r3, 4
-; P9BE-DAG: lfiwzx f0, 0, r3
-; P9BE-DAG: xxspltw v2, v2, 1
-; P9BE: xxsldwi v3, f0, f0, 1
-; P9BE: vmrghw v2, v3, v2
+; P9BE-NEXT: addi r3, r3, 4
+; P9BE-NEXT: xxspltw v2, v2, 1
+; P9BE-NEXT: lfiwzx f0, 0, r3
+; P9BE-NEXT: xxsldwi v3, f0, f0, 1
+; P9BE-NEXT: vmrghw v2, v3, v2
; P9BE-NEXT: blr
-
+;
; P8LE-LABEL: s2v_test_f4:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: vmrglw v2, v2, v2
@@ -272,7 +361,7 @@ define <2 x float> @s2v_test_f4(float* nocapture readonly %f64, <2 x float> %vec
; P8LE-NEXT: lxsiwzx v3, 0, r3
; P8LE-NEXT: vmrghw v2, v2, v3
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test_f4:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addi r3, r3, 4
@@ -296,22 +385,22 @@ define <2 x float> @s2v_test_f5(<2 x float> %vec, float* nocapture readonly %ptr
; P9LE-NEXT: vmrglw v2, v2, v2
; P9LE-NEXT: vmrghw v2, v2, v3
; P9LE-NEXT: blr
-
+;
; P9BE-LABEL: s2v_test_f5:
; P9BE: # %bb.0: # %entry
-; P9BE: lfiwzx f0, 0, r5
-; P9BE: xxspltw v2, v2, 1
+; P9BE-NEXT: lfiwzx f0, 0, r5
+; P9BE-NEXT: xxspltw v2, v2, 1
; P9BE-NEXT: xxsldwi v3, f0, f0, 1
-; P9BE: vmrghw v2, v3, v2
+; P9BE-NEXT: vmrghw v2, v3, v2
; P9BE-NEXT: blr
-
+;
; P8LE-LABEL: s2v_test_f5:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: vmrglw v2, v2, v2
; P8LE-NEXT: lxsiwzx v3, 0, r5
; P8LE-NEXT: vmrghw v2, v2, v3
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test_f5:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lfiwzx f0, 0, r5
diff --git a/llvm/test/CodeGen/PowerPC/toc-float.ll b/llvm/test/CodeGen/PowerPC/toc-float.ll
index 5ecc6a5c6821..a9b12647b3b6 100644
--- a/llvm/test/CodeGen/PowerPC/toc-float.ll
+++ b/llvm/test/CodeGen/PowerPC/toc-float.ll
@@ -1,57 +1,80 @@
-; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 <%s | FileCheck -check-prefix=CHECK-P9 %s
-; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 <%s | FileCheck -check-prefix=CHECK-P8 %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-P9 %s
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck -check-prefix=CHECK-P8 %s
; As the constant could be represented as float, a float is
; loaded from constant pool.
define double @doubleConstant1() {
- ret double 1.400000e+01
-
; CHECK-P9-LABEL: doubleConstant1:
-; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
-; CHECK-P9: lfs {{[0-9]+}}, [[VAR]]@toc at l([[REG1]])
+; CHECK-P9: # %bb.0:
+; CHECK-P9-NEXT: addis 3, 2, .LCPI0_0 at toc@ha
+; CHECK-P9-NEXT: lfs 1, .LCPI0_0 at toc@l(3)
+; CHECK-P9-NEXT: blr
+;
; CHECK-P8-LABEL: doubleConstant1:
-; CHECK-P8: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
-; CHECK-P8: lfs {{[0-9]+}}, [[VAR]]@toc at l([[REG1]])
+; CHECK-P8: # %bb.0:
+; CHECK-P8-NEXT: addis 3, 2, .LCPI0_0 at toc@ha
+; CHECK-P8-NEXT: lfs 1, .LCPI0_0 at toc@l(3)
+; CHECK-P8-NEXT: blr
+ ret double 1.400000e+01
}
; As the constant couldn't be represented as float, a double is
; loaded from constant pool.
define double @doubleConstant2() {
- ret double 2.408904e+01
-
; CHECK-P9-LABEL: doubleConstant2:
-; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
-; CHECK-P9: lfd {{[0-9]+}}, [[VAR]]@toc at l([[REG1]])
+; CHECK-P9: # %bb.0:
+; CHECK-P9-NEXT: addis 3, 2, .LCPI1_0 at toc@ha
+; CHECK-P9-NEXT: lfd 1, .LCPI1_0 at toc@l(3)
+; CHECK-P9-NEXT: blr
+;
; CHECK-P8-LABEL: doubleConstant2:
-; CHECK-P8: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
-; CHECK-P8: lfd {{[0-9]+}}, [[VAR]]@toc at l([[REG1]])
+; CHECK-P8: # %bb.0:
+; CHECK-P8-NEXT: addis 3, 2, .LCPI1_0 at toc@ha
+; CHECK-P8-NEXT: lfd 1, .LCPI1_0 at toc@l(3)
+; CHECK-P8-NEXT: blr
+ ret double 2.408904e+01
}
@FArr = hidden local_unnamed_addr global [10 x float] zeroinitializer, align 4
define float @floatConstantArray() local_unnamed_addr {
+; CHECK-P9-LABEL: floatConstantArray:
+; CHECK-P9: # %bb.0:
+; CHECK-P9-NEXT: addis 3, 2, FArr at toc@ha+12
+; CHECK-P9-NEXT: lfs 0, FArr at toc@l+12(3)
+; CHECK-P9-NEXT: addis 3, 2, .LCPI2_0 at toc@ha
+; CHECK-P9-NEXT: lfs 1, .LCPI2_0 at toc@l(3)
+; CHECK-P9-NEXT: xsaddsp 1, 0, 1
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: floatConstantArray:
+; CHECK-P8: # %bb.0:
+; CHECK-P8-NEXT: addis 3, 2, FArr at toc@ha
+; CHECK-P8-NEXT: addis 4, 2, .LCPI2_0 at toc@ha
+; CHECK-P8-NEXT: addi 3, 3, FArr at toc@l
+; CHECK-P8-NEXT: lfs 1, .LCPI2_0 at toc@l(4)
+; CHECK-P8-NEXT: lfs 0, 12(3)
+; CHECK-P8-NEXT: xsaddsp 1, 0, 1
+; CHECK-P8-NEXT: blr
%1 = load float, float* getelementptr inbounds ([10 x float], [10 x float]* @FArr, i64 0, i64 3), align 4
%2 = fadd float %1, 0x400B333340000000
ret float %2
-
-; CHECK-P9-LABEL: floatConstantArray
-; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha+[[REG2:[0-9]+]]
-; CHECK-P9: lfs {{[0-9]+}}, [[VAR]]@toc at l+[[REG2]]([[REG1]])
-; CHECK-P8-LABEL: floatConstantArray
-; CHECK-P8: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
-; CHECK-P8: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc at l
-; CHECK-P8: lfs {{[0-9]+}}, 12([[REG2]])
}
define float @floatConstant() {
- ret float 0x400470A3E0000000
-
; CHECK-P9-LABEL: floatConstant:
-; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
-; CHECK-P9: lfs {{[0-9]+}}, [[VAR]]@toc at l([[REG1]])
+; CHECK-P9: # %bb.0:
+; CHECK-P9-NEXT: addis 3, 2, .LCPI3_0 at toc@ha
+; CHECK-P9-NEXT: lfs 1, .LCPI3_0 at toc@l(3)
+; CHECK-P9-NEXT: blr
+;
; CHECK-P8-LABEL: floatConstant:
-; CHECK-P8: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
-; CHECK-P8: lfs {{[0-9]+}}, [[VAR]]@toc at l([[REG1]])
+; CHECK-P8: # %bb.0:
+; CHECK-P8-NEXT: addis 3, 2, .LCPI3_0 at toc@ha
+; CHECK-P8-NEXT: lfs 1, .LCPI3_0 at toc@l(3)
+; CHECK-P8-NEXT: blr
+ ret float 0x400470A3E0000000
}
; llvm put the hidden globals into the TOC table.
@@ -59,55 +82,79 @@ define float @floatConstant() {
@d = hidden local_unnamed_addr global [200 x double] zeroinitializer, align 8
define double @doubleConstantArray() {
+; CHECK-P9-LABEL: doubleConstantArray:
+; CHECK-P9: # %bb.0:
+; CHECK-P9-NEXT: addis 3, 2, d at toc@ha+24
+; CHECK-P9-NEXT: lfd 0, d at toc@l+24(3)
+; CHECK-P9-NEXT: addis 3, 2, .LCPI4_0 at toc@ha
+; CHECK-P9-NEXT: lfd 1, .LCPI4_0 at toc@l(3)
+; CHECK-P9-NEXT: xsadddp 1, 0, 1
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: doubleConstantArray:
+; CHECK-P8: # %bb.0:
+; CHECK-P8-NEXT: addis 3, 2, d at toc@ha
+; CHECK-P8-NEXT: addis 4, 2, .LCPI4_0 at toc@ha
+; CHECK-P8-NEXT: addi 3, 3, d at toc@l
+; CHECK-P8-NEXT: lfd 1, .LCPI4_0 at toc@l(4)
+; CHECK-P8-NEXT: lfd 0, 24(3)
+; CHECK-P8-NEXT: xsadddp 1, 0, 1
+; CHECK-P8-NEXT: blr
%1 = load double, double* getelementptr inbounds ([200 x double], [200 x double]* @d, i64 0, i64 3), align 8
%2 = fadd double %1, 6.880000e+00
ret double %2
-
-; CHECK-P9-LABEL: doubleConstantArray
-; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha+[[REG2:[0-9]+]]
-; CHECK-P9: lfd {{[0-9]+}}, [[VAR]]@toc at l+[[REG2]]([[REG1]])
-; CHECK-P8-LABEL: doubleConstantArray
-; CHECK-P8: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
-; CHECK-P8: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc at l
-; CHECK-P8: lfd {{[0-9]+}}, 24([[REG2]])
}
@arr = hidden local_unnamed_addr global [20000 x double] zeroinitializer, align 8
+; Access an element with an offset that doesn't fit in the displacement field of LFD.
define double @doubleLargeConstantArray() {
+; CHECK-P9-LABEL: doubleLargeConstantArray:
+; CHECK-P9: # %bb.0:
+; CHECK-P9-NEXT: addis 3, 2, arr at toc@ha
+; CHECK-P9-NEXT: li 4, 0
+; CHECK-P9-NEXT: addi 3, 3, arr at toc@l
+; CHECK-P9-NEXT: ori 4, 4, 32768
+; CHECK-P9-NEXT: lfdx 0, 3, 4
+; CHECK-P9-NEXT: addis 3, 2, .LCPI5_0 at toc@ha
+; CHECK-P9-NEXT: lfd 1, .LCPI5_0 at toc@l(3)
+; CHECK-P9-NEXT: xsadddp 1, 0, 1
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: doubleLargeConstantArray:
+; CHECK-P8: # %bb.0:
+; CHECK-P8-NEXT: addis 3, 2, arr at toc@ha
+; CHECK-P8-NEXT: li 4, 0
+; CHECK-P8-NEXT: addis 5, 2, .LCPI5_0 at toc@ha
+; CHECK-P8-NEXT: addi 3, 3, arr at toc@l
+; CHECK-P8-NEXT: ori 4, 4, 32768
+; CHECK-P8-NEXT: lfdx 0, 3, 4
+; CHECK-P8-NEXT: lfd 1, .LCPI5_0 at toc@l(5)
+; CHECK-P8-NEXT: xsadddp 1, 0, 1
+; CHECK-P8-NEXT: blr
%1 = load double, double* getelementptr inbounds ([20000 x double], [20000 x double]* @arr, i64 0, i64 4096), align 8
%2 = fadd double %1, 6.880000e+00
ret double %2
-
-; Access an element with an offset that doesn't fit in the displacement field of LFD.
-; CHECK-P9-LABEL: doubleLargeConstantArray
-; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
-; CHECK-P9: li [[REG2:[0-9]+]], 0
-; CHECK-P9: addi [[REG3:[0-9]+]], [[REG1]], [[VAR:[a-z0-9A-Z_.]+]]@toc at l
-; CHECK-P9: ori [[REG4:[0-9]+]], [[REG2]], 32768
-; CHECK-P9: lfdx {{[0-9]+}}, [[REG3]], [[REG4]]
-; CHECK-P8-LABEL: doubleLargeConstantArray
-; CHECK-P8: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
-; CHECK-P8: li [[REG2:[0-9]+]], 0
-; CHECK-P8: addi [[REG3:[0-9]+]], [[REG1]], [[VAR:[a-z0-9A-Z_.]+]]@toc at l
-; CHECK-P8: ori [[REG4:[0-9]+]], [[REG2]], 32768
-; CHECK-P8: lfdx {{[0-9]+}}, [[REG3]], [[REG4]]
}
@vec_arr = global [10 x <4 x i32>] zeroinitializer, align 16
define <4 x i32> @vectorArray() #0 {
+; CHECK-P9-LABEL: vectorArray:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: addis 3, 2, .LC0 at toc@ha
+; CHECK-P9-NEXT: ld 3, .LC0 at toc@l(3)
+; CHECK-P9-NEXT: lxv 34, 32(3)
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: vectorArray:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: addis 3, 2, .LC0 at toc@ha
+; CHECK-P8-NEXT: ld 3, .LC0 at toc@l(3)
+; CHECK-P8-NEXT: addi 3, 3, 32
+; CHECK-P8-NEXT: lvx 2, 0, 3
+; CHECK-P8-NEXT: blr
entry:
%0 = load <4 x i32>, <4 x i32>* getelementptr inbounds ([10 x <4 x i32>], [10 x <4 x i32>]* @vec_arr, i64 0, i64 2), align 16
ret <4 x i32> %0
-
-; CHECK-P9-LABEL: vectorArray
-; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
-; CHECK-P9: ld [[REG2:[0-9]+]], [[VAR]]@toc at l([[REG1]])
-; CHECK-P9: lxv {{[0-9]+}}, 32([[REG2]])
-; CHECK-P8-LABEL: vectorArray
-; CHECK-P8: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
-; CHECK-P8: ld [[REG2:[0-9]+]], [[VAR]]@toc at l([[REG1]])
-; CHECK-P8: addi [[REG3:[0-9]+]], [[REG2]], 32
-; CHECK-P8: lvx {{[0-9]+}}, 0, [[REG3]]
}
diff --git a/llvm/test/CodeGen/PowerPC/vec-itofp.ll b/llvm/test/CodeGen/PowerPC/vec-itofp.ll
index d9528e235743..2eee272c71b9 100644
--- a/llvm/test/CodeGen/PowerPC/vec-itofp.ll
+++ b/llvm/test/CodeGen/PowerPC/vec-itofp.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P8
@@ -9,184 +10,458 @@
; RUN: FileCheck %s --check-prefix=CHECK-BE
define void @test8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) {
+; CHECK-P8-LABEL: test8:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: addis r5, r2, .LCPI0_0 at toc@ha
+; CHECK-P8-NEXT: addis r6, r2, .LCPI0_2 at toc@ha
+; CHECK-P8-NEXT: lvx v3, 0, r4
+; CHECK-P8-NEXT: addis r4, r2, .LCPI0_1 at toc@ha
+; CHECK-P8-NEXT: xxlxor v4, v4, v4
+; CHECK-P8-NEXT: addi r5, r5, .LCPI0_0 at toc@l
+; CHECK-P8-NEXT: addi r6, r6, .LCPI0_2 at toc@l
+; CHECK-P8-NEXT: addi r4, r4, .LCPI0_1 at toc@l
+; CHECK-P8-NEXT: lvx v2, 0, r5
+; CHECK-P8-NEXT: addis r5, r2, .LCPI0_3 at toc@ha
+; CHECK-P8-NEXT: lvx v5, 0, r6
+; CHECK-P8-NEXT: lvx v1, 0, r4
+; CHECK-P8-NEXT: li r4, 48
+; CHECK-P8-NEXT: addi r5, r5, .LCPI0_3 at toc@l
+; CHECK-P8-NEXT: lvx v0, 0, r5
+; CHECK-P8-NEXT: li r5, 32
+; CHECK-P8-NEXT: vperm v2, v4, v3, v2
+; CHECK-P8-NEXT: vperm v5, v4, v3, v5
+; CHECK-P8-NEXT: vperm v0, v4, v3, v0
+; CHECK-P8-NEXT: vperm v3, v4, v3, v1
+; CHECK-P8-NEXT: xvcvuxddp vs0, v2
+; CHECK-P8-NEXT: xvcvuxddp vs1, v5
+; CHECK-P8-NEXT: xvcvuxddp vs2, v0
+; CHECK-P8-NEXT: xvcvuxddp vs3, v3
+; CHECK-P8-NEXT: xxswapd vs0, vs0
+; CHECK-P8-NEXT: xxswapd vs1, vs1
+; CHECK-P8-NEXT: xxswapd vs2, vs2
+; CHECK-P8-NEXT: xxswapd vs3, vs3
+; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
+; CHECK-P8-NEXT: li r4, 16
+; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
+; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
+; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
+; CHECK-P8-NEXT: blr
+;
+; CHECK-P9-LABEL: test8:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: lxv v2, 0(r4)
+; CHECK-P9-NEXT: addis r4, r2, .LCPI0_0 at toc@ha
+; CHECK-P9-NEXT: xxlxor v4, v4, v4
+; CHECK-P9-NEXT: addi r4, r4, .LCPI0_0 at toc@l
+; CHECK-P9-NEXT: lxvx v3, 0, r4
+; CHECK-P9-NEXT: addis r4, r2, .LCPI0_1 at toc@ha
+; CHECK-P9-NEXT: addi r4, r4, .LCPI0_1 at toc@l
+; CHECK-P9-NEXT: vperm v3, v4, v2, v3
+; CHECK-P9-NEXT: xvcvuxddp vs0, v3
+; CHECK-P9-NEXT: lxvx v3, 0, r4
+; CHECK-P9-NEXT: addis r4, r2, .LCPI0_2 at toc@ha
+; CHECK-P9-NEXT: addi r4, r4, .LCPI0_2 at toc@l
+; CHECK-P9-NEXT: vperm v3, v4, v2, v3
+; CHECK-P9-NEXT: stxv vs0, 0(r3)
+; CHECK-P9-NEXT: xvcvuxddp vs1, v3
+; CHECK-P9-NEXT: lxvx v3, 0, r4
+; CHECK-P9-NEXT: addis r4, r2, .LCPI0_3 at toc@ha
+; CHECK-P9-NEXT: addi r4, r4, .LCPI0_3 at toc@l
+; CHECK-P9-NEXT: vperm v3, v4, v2, v3
+; CHECK-P9-NEXT: stxv vs1, 16(r3)
+; CHECK-P9-NEXT: xvcvuxddp vs2, v3
+; CHECK-P9-NEXT: lxvx v3, 0, r4
+; CHECK-P9-NEXT: vperm v2, v4, v2, v3
+; CHECK-P9-NEXT: stxv vs2, 32(r3)
+; CHECK-P9-NEXT: xvcvuxddp vs3, v2
+; CHECK-P9-NEXT: stxv vs3, 48(r3)
+; CHECK-P9-NEXT: blr
+;
+; CHECK-BE-LABEL: test8:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: lxv v2, 0(r4)
+; CHECK-BE-NEXT: addis r4, r2, .LCPI0_0 at toc@ha
+; CHECK-BE-NEXT: xxlxor v4, v4, v4
+; CHECK-BE-NEXT: addi r4, r4, .LCPI0_0 at toc@l
+; CHECK-BE-NEXT: lxvx v3, 0, r4
+; CHECK-BE-NEXT: addis r4, r2, .LCPI0_1 at toc@ha
+; CHECK-BE-NEXT: addi r4, r4, .LCPI0_1 at toc@l
+; CHECK-BE-NEXT: vperm v3, v2, v4, v3
+; CHECK-BE-NEXT: xvcvuxddp vs0, v3
+; CHECK-BE-NEXT: lxvx v3, 0, r4
+; CHECK-BE-NEXT: addis r4, r2, .LCPI0_2 at toc@ha
+; CHECK-BE-NEXT: addi r4, r4, .LCPI0_2 at toc@l
+; CHECK-BE-NEXT: vperm v3, v4, v2, v3
+; CHECK-BE-NEXT: stxv vs0, 0(r3)
+; CHECK-BE-NEXT: xvcvuxddp vs1, v3
+; CHECK-BE-NEXT: lxvx v3, 0, r4
+; CHECK-BE-NEXT: addis r4, r2, .LCPI0_3 at toc@ha
+; CHECK-BE-NEXT: addi r4, r4, .LCPI0_3 at toc@l
+; CHECK-BE-NEXT: vperm v3, v4, v2, v3
+; CHECK-BE-NEXT: stxv vs1, 16(r3)
+; CHECK-BE-NEXT: xvcvuxddp vs2, v3
+; CHECK-BE-NEXT: lxvx v3, 0, r4
+; CHECK-BE-NEXT: vperm v2, v4, v2, v3
+; CHECK-BE-NEXT: stxv vs2, 32(r3)
+; CHECK-BE-NEXT: xvcvuxddp vs3, v2
+; CHECK-BE-NEXT: stxv vs3, 48(r3)
+; CHECK-BE-NEXT: blr
entry:
%0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16
%1 = uitofp <8 x i16> %0 to <8 x double>
store <8 x double> %1, <8 x double>* %Sink, align 16
ret void
-; CHECK-P9-LABEL: @test8
-; CHECK-P9: vperm
-; CHECK-P9: xvcvuxddp
-; CHECK-P9: vperm
-; CHECK-P9: xvcvuxddp
-; CHECK-P9: vperm
-; CHECK-P9: xvcvuxddp
-; CHECK-P9: vperm
-; CHECK-P9: xvcvuxddp
-; CHECK-P8-LABEL: @test8
-; CHECK-P8: vperm
-; CHECK-P8: vperm
-; CHECK-P8: vperm
-; CHECK-P8: vperm
-; CHECK-P8: xvcvuxddp
-; CHECK-P8: xvcvuxddp
-; CHECK-P8: xvcvuxddp
-; CHECK-P8: xvcvuxddp
}
define void @test4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) {
+; CHECK-P8-LABEL: test4:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0 at toc@ha
+; CHECK-P8-NEXT: addis r6, r2, .LCPI1_1 at toc@ha
+; CHECK-P8-NEXT: lvx v3, 0, r4
+; CHECK-P8-NEXT: xxlxor v4, v4, v4
+; CHECK-P8-NEXT: li r4, 16
+; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0 at toc@l
+; CHECK-P8-NEXT: lvx v2, 0, r5
+; CHECK-P8-NEXT: addi r5, r6, .LCPI1_1 at toc@l
+; CHECK-P8-NEXT: lvx v5, 0, r5
+; CHECK-P8-NEXT: vperm v2, v4, v3, v2
+; CHECK-P8-NEXT: vperm v3, v4, v3, v5
+; CHECK-P8-NEXT: xvcvuxddp vs0, v2
+; CHECK-P8-NEXT: xvcvuxddp vs1, v3
+; CHECK-P8-NEXT: xxswapd vs0, vs0
+; CHECK-P8-NEXT: xxswapd vs1, vs1
+; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
+; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
+; CHECK-P8-NEXT: blr
+;
+; CHECK-P9-LABEL: test4:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: lxv v2, 0(r4)
+; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0 at toc@ha
+; CHECK-P9-NEXT: xxlxor v4, v4, v4
+; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0 at toc@l
+; CHECK-P9-NEXT: lxvx v3, 0, r4
+; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1 at toc@ha
+; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1 at toc@l
+; CHECK-P9-NEXT: vperm v3, v4, v2, v3
+; CHECK-P9-NEXT: xvcvuxddp vs0, v3
+; CHECK-P9-NEXT: lxvx v3, 0, r4
+; CHECK-P9-NEXT: vperm v2, v4, v2, v3
+; CHECK-P9-NEXT: stxv vs0, 0(r3)
+; CHECK-P9-NEXT: xvcvuxddp vs1, v2
+; CHECK-P9-NEXT: stxv vs1, 16(r3)
+; CHECK-P9-NEXT: blr
+;
+; CHECK-BE-LABEL: test4:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: lxv v2, 0(r4)
+; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0 at toc@ha
+; CHECK-BE-NEXT: xxlxor v4, v4, v4
+; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0 at toc@l
+; CHECK-BE-NEXT: lxvx v3, 0, r4
+; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1 at toc@ha
+; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1 at toc@l
+; CHECK-BE-NEXT: vperm v3, v2, v4, v3
+; CHECK-BE-NEXT: xvcvuxddp vs0, v3
+; CHECK-BE-NEXT: lxvx v3, 0, r4
+; CHECK-BE-NEXT: vperm v2, v4, v2, v3
+; CHECK-BE-NEXT: stxv vs0, 0(r3)
+; CHECK-BE-NEXT: xvcvuxddp vs1, v2
+; CHECK-BE-NEXT: stxv vs1, 16(r3)
+; CHECK-BE-NEXT: blr
entry:
%0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16
%1 = uitofp <4 x i16> %0 to <4 x double>
store <4 x double> %1, <4 x double>* %Sink, align 16
ret void
-; CHECK-P9-LABEL: @test4
-; CHECK-P9: vperm
-; CHECK-P9: xvcvuxddp
-; CHECK-P9: vperm
-; CHECK-P9: xvcvuxddp
-; CHECK-P8-LABEL: @test4
-; CHECK-P8: vperm
-; CHECK-P8: vperm
-; CHECK-P8: xvcvuxddp
-; CHECK-P8: xvcvuxddp
}
define void @test2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) {
+; CHECK-P8-LABEL: test2:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0 at toc@ha
+; CHECK-P8-NEXT: lvx v3, 0, r4
+; CHECK-P8-NEXT: xxlxor v4, v4, v4
+; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0 at toc@l
+; CHECK-P8-NEXT: lvx v2, 0, r5
+; CHECK-P8-NEXT: vperm v2, v4, v3, v2
+; CHECK-P8-NEXT: xvcvuxddp vs0, v2
+; CHECK-P8-NEXT: xxswapd vs0, vs0
+; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
+; CHECK-P8-NEXT: blr
+;
+; CHECK-P9-LABEL: test2:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: lxv v2, 0(r4)
+; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0 at toc@ha
+; CHECK-P9-NEXT: xxlxor v4, v4, v4
+; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0 at toc@l
+; CHECK-P9-NEXT: lxvx v3, 0, r4
+; CHECK-P9-NEXT: vperm v2, v4, v2, v3
+; CHECK-P9-NEXT: xvcvuxddp vs0, v2
+; CHECK-P9-NEXT: stxv vs0, 0(r3)
+; CHECK-P9-NEXT: blr
+;
+; CHECK-BE-LABEL: test2:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: lxv v2, 0(r4)
+; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0 at toc@ha
+; CHECK-BE-NEXT: xxlxor v4, v4, v4
+; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0 at toc@l
+; CHECK-BE-NEXT: lxvx v3, 0, r4
+; CHECK-BE-NEXT: vperm v2, v2, v4, v3
+; CHECK-BE-NEXT: xvcvuxddp vs0, v2
+; CHECK-BE-NEXT: stxv vs0, 0(r3)
+; CHECK-BE-NEXT: blr
entry:
%0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16
%1 = uitofp <2 x i16> %0 to <2 x double>
store <2 x double> %1, <2 x double>* %Sink, align 16
ret void
-; CHECK-P9-LABEL: .LCPI2_0:
-; CHECK-P9-NEXT: .byte 31
-; CHECK-P9-NEXT: .byte 30
-; CHECK-P9-NEXT: .byte 13
-; CHECK-P9-NEXT: .byte 12
-; CHECK-P9-NEXT: .byte 11
-; CHECK-P9-NEXT: .byte 10
-; CHECK-P9-NEXT: .byte 9
-; CHECK-P9-NEXT: .byte 8
-; CHECK-P9-NEXT: .byte 29
-; CHECK-P9-NEXT: .byte 28
-; CHECK-P9-NEXT: .byte 5
-; CHECK-P9-NEXT: .byte 4
-; CHECK-P9-NEXT: .byte 3
-; CHECK-P9-NEXT: .byte 2
-; CHECK-P9-NEXT: .byte 1
-; CHECK-P9-NEXT: .byte 0
-; CHECK-P9: addi [[REG1:r[0-9]+]], {{r[0-9]+}}, .LCPI2_0 at toc@l
-; CHECK-P9: lxvx [[REG2:v[0-9]+]], 0, [[REG1]]
-; CHECK-P9: vperm [[REG3:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, [[REG2]]
-; CHECK-P9: xvcvuxddp {{vs[0-9]+}}, [[REG3]]
-; CHECK-P8-LABEL: @test2
-; CHECK-P8: vperm [[REG1:v[0-9]+]]
-; CHECK-P8: xvcvuxddp {{vs[0-9]+}}, [[REG1]]
-; CHECK-BE-LABEL: .LCPI2_0:
-; CHECK-BE-NEXT: .byte 16
-; CHECK-BE-NEXT: .byte 17
-; CHECK-BE-NEXT: .byte 18
-; CHECK-BE-NEXT: .byte 19
-; CHECK-BE-NEXT: .byte 20
-; CHECK-BE-NEXT: .byte 21
-; CHECK-BE-NEXT: .byte 0
-; CHECK-BE-NEXT: .byte 1
-; CHECK-BE-NEXT: .byte 24
-; CHECK-BE-NEXT: .byte 25
-; CHECK-BE-NEXT: .byte 26
-; CHECK-BE-NEXT: .byte 27
-; CHECK-BE-NEXT: .byte 28
-; CHECK-BE-NEXT: .byte 29
-; CHECK-BE-NEXT: .byte 2
-; CHECK-BE-NEXT: .byte 3
-; CHECK-BE: addi [[REG1:r[0-9]+]], {{r[0-9]+}}, .LCPI2_0 at toc@l
-; CHECK-BE: lxvx [[REG2:v[0-9]+]], 0, [[REG1]]
-; CHECK-BE: vperm [[REG3:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, [[REG2]]
-; CHECK-BE: xvcvuxddp {{vs[0-9]+}}, [[REG3]]
}
define void @stest8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) {
+; CHECK-P8-LABEL: stest8:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: addis r5, r2, .LCPI3_0 at toc@ha
+; CHECK-P8-NEXT: addis r6, r2, .LCPI3_2 at toc@ha
+; CHECK-P8-NEXT: lvx v3, 0, r4
+; CHECK-P8-NEXT: addis r4, r2, .LCPI3_1 at toc@ha
+; CHECK-P8-NEXT: addi r5, r5, .LCPI3_0 at toc@l
+; CHECK-P8-NEXT: addi r6, r6, .LCPI3_2 at toc@l
+; CHECK-P8-NEXT: addi r4, r4, .LCPI3_1 at toc@l
+; CHECK-P8-NEXT: lvx v2, 0, r5
+; CHECK-P8-NEXT: addis r5, r2, .LCPI3_3 at toc@ha
+; CHECK-P8-NEXT: lvx v4, 0, r6
+; CHECK-P8-NEXT: addis r6, r2, .LCPI3_4 at toc@ha
+; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
+; CHECK-P8-NEXT: li r4, 48
+; CHECK-P8-NEXT: addi r5, r5, .LCPI3_3 at toc@l
+; CHECK-P8-NEXT: lvx v5, 0, r5
+; CHECK-P8-NEXT: addi r5, r6, .LCPI3_4 at toc@l
+; CHECK-P8-NEXT: lvx v0, 0, r5
+; CHECK-P8-NEXT: vperm v2, v3, v3, v2
+; CHECK-P8-NEXT: li r5, 32
+; CHECK-P8-NEXT: vperm v4, v3, v3, v4
+; CHECK-P8-NEXT: vperm v5, v3, v3, v5
+; CHECK-P8-NEXT: vperm v3, v3, v3, v0
+; CHECK-P8-NEXT: xxswapd v0, vs0
+; CHECK-P8-NEXT: vsld v2, v2, v0
+; CHECK-P8-NEXT: vsld v4, v4, v0
+; CHECK-P8-NEXT: vsld v5, v5, v0
+; CHECK-P8-NEXT: vsld v3, v3, v0
+; CHECK-P8-NEXT: vsrad v2, v2, v0
+; CHECK-P8-NEXT: vsrad v3, v3, v0
+; CHECK-P8-NEXT: vsrad v4, v4, v0
+; CHECK-P8-NEXT: vsrad v5, v5, v0
+; CHECK-P8-NEXT: xvcvsxddp vs2, v3
+; CHECK-P8-NEXT: xvcvsxddp vs0, v2
+; CHECK-P8-NEXT: xvcvsxddp vs1, v5
+; CHECK-P8-NEXT: xvcvsxddp vs3, v4
+; CHECK-P8-NEXT: xxswapd vs2, vs2
+; CHECK-P8-NEXT: xxswapd vs0, vs0
+; CHECK-P8-NEXT: xxswapd vs1, vs1
+; CHECK-P8-NEXT: xxswapd vs3, vs3
+; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
+; CHECK-P8-NEXT: li r4, 16
+; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
+; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
+; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
+; CHECK-P8-NEXT: blr
+;
+; CHECK-P9-LABEL: stest8:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: lxv v2, 0(r4)
+; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0 at toc@ha
+; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0 at toc@l
+; CHECK-P9-NEXT: lxvx v3, 0, r4
+; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1 at toc@ha
+; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1 at toc@l
+; CHECK-P9-NEXT: vperm v3, v2, v2, v3
+; CHECK-P9-NEXT: vextsh2d v3, v3
+; CHECK-P9-NEXT: xvcvsxddp vs0, v3
+; CHECK-P9-NEXT: lxvx v3, 0, r4
+; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2 at toc@ha
+; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2 at toc@l
+; CHECK-P9-NEXT: vperm v3, v2, v2, v3
+; CHECK-P9-NEXT: stxv vs0, 0(r3)
+; CHECK-P9-NEXT: vextsh2d v3, v3
+; CHECK-P9-NEXT: xvcvsxddp vs1, v3
+; CHECK-P9-NEXT: lxvx v3, 0, r4
+; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3 at toc@ha
+; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3 at toc@l
+; CHECK-P9-NEXT: vperm v3, v2, v2, v3
+; CHECK-P9-NEXT: stxv vs1, 16(r3)
+; CHECK-P9-NEXT: vextsh2d v3, v3
+; CHECK-P9-NEXT: xvcvsxddp vs2, v3
+; CHECK-P9-NEXT: lxvx v3, 0, r4
+; CHECK-P9-NEXT: vperm v2, v2, v2, v3
+; CHECK-P9-NEXT: stxv vs2, 32(r3)
+; CHECK-P9-NEXT: vextsh2d v2, v2
+; CHECK-P9-NEXT: xvcvsxddp vs3, v2
+; CHECK-P9-NEXT: stxv vs3, 48(r3)
+; CHECK-P9-NEXT: blr
+;
+; CHECK-BE-LABEL: stest8:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: lxv v2, 0(r4)
+; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0 at toc@ha
+; CHECK-BE-NEXT: xxlxor v4, v4, v4
+; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0 at toc@l
+; CHECK-BE-NEXT: lxvx v3, 0, r4
+; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1 at toc@ha
+; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1 at toc@l
+; CHECK-BE-NEXT: vperm v3, v4, v2, v3
+; CHECK-BE-NEXT: vextsh2d v3, v3
+; CHECK-BE-NEXT: xvcvsxddp vs0, v3
+; CHECK-BE-NEXT: lxvx v3, 0, r4
+; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2 at toc@ha
+; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2 at toc@l
+; CHECK-BE-NEXT: vperm v3, v4, v2, v3
+; CHECK-BE-NEXT: stxv vs0, 16(r3)
+; CHECK-BE-NEXT: vextsh2d v3, v3
+; CHECK-BE-NEXT: xvcvsxddp vs1, v3
+; CHECK-BE-NEXT: lxvx v3, 0, r4
+; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3 at toc@ha
+; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3 at toc@l
+; CHECK-BE-NEXT: vperm v3, v2, v2, v3
+; CHECK-BE-NEXT: stxv vs1, 48(r3)
+; CHECK-BE-NEXT: vextsh2d v3, v3
+; CHECK-BE-NEXT: xvcvsxddp vs2, v3
+; CHECK-BE-NEXT: lxvx v3, 0, r4
+; CHECK-BE-NEXT: vperm v2, v2, v2, v3
+; CHECK-BE-NEXT: stxv vs2, 0(r3)
+; CHECK-BE-NEXT: vextsh2d v2, v2
+; CHECK-BE-NEXT: xvcvsxddp vs3, v2
+; CHECK-BE-NEXT: stxv vs3, 32(r3)
+; CHECK-BE-NEXT: blr
entry:
%0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16
%1 = sitofp <8 x i16> %0 to <8 x double>
store <8 x double> %1, <8 x double>* %Sink, align 16
ret void
-; CHECK-P9-LABEL: @stest8
-; CHECK-P9: vperm
-; CHECK-P9: vextsh2d
-; CHECK-P9: xvcvsxddp
-; CHECK-P9: vperm
-; CHECK-P9: vextsh2d
-; CHECK-P9: xvcvsxddp
-; CHECK-P9: vperm
-; CHECK-P9: vextsh2d
-; CHECK-P9: xvcvsxddp
-; CHECK-P9: vperm
-; CHECK-P9: vextsh2d
-; CHECK-P9: xvcvsxddp
}
define void @stest4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) {
+; CHECK-P8-LABEL: stest4:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: addis r5, r2, .LCPI4_0 at toc@ha
+; CHECK-P8-NEXT: addis r6, r2, .LCPI4_2 at toc@ha
+; CHECK-P8-NEXT: lvx v3, 0, r4
+; CHECK-P8-NEXT: addis r4, r2, .LCPI4_1 at toc@ha
+; CHECK-P8-NEXT: addi r5, r5, .LCPI4_0 at toc@l
+; CHECK-P8-NEXT: addi r4, r4, .LCPI4_1 at toc@l
+; CHECK-P8-NEXT: lvx v2, 0, r5
+; CHECK-P8-NEXT: addi r5, r6, .LCPI4_2 at toc@l
+; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
+; CHECK-P8-NEXT: li r4, 16
+; CHECK-P8-NEXT: lvx v4, 0, r5
+; CHECK-P8-NEXT: vperm v2, v3, v3, v2
+; CHECK-P8-NEXT: vperm v3, v3, v3, v4
+; CHECK-P8-NEXT: xxswapd v4, vs0
+; CHECK-P8-NEXT: vsld v2, v2, v4
+; CHECK-P8-NEXT: vsld v3, v3, v4
+; CHECK-P8-NEXT: vsrad v2, v2, v4
+; CHECK-P8-NEXT: vsrad v3, v3, v4
+; CHECK-P8-NEXT: xvcvsxddp vs0, v2
+; CHECK-P8-NEXT: xvcvsxddp vs1, v3
+; CHECK-P8-NEXT: xxswapd vs0, vs0
+; CHECK-P8-NEXT: xxswapd vs1, vs1
+; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
+; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
+; CHECK-P8-NEXT: blr
+;
+; CHECK-P9-LABEL: stest4:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: lxv v2, 0(r4)
+; CHECK-P9-NEXT: addis r4, r2, .LCPI4_0 at toc@ha
+; CHECK-P9-NEXT: addi r4, r4, .LCPI4_0 at toc@l
+; CHECK-P9-NEXT: lxvx v3, 0, r4
+; CHECK-P9-NEXT: addis r4, r2, .LCPI4_1 at toc@ha
+; CHECK-P9-NEXT: addi r4, r4, .LCPI4_1 at toc@l
+; CHECK-P9-NEXT: vperm v3, v2, v2, v3
+; CHECK-P9-NEXT: vextsh2d v3, v3
+; CHECK-P9-NEXT: xvcvsxddp vs0, v3
+; CHECK-P9-NEXT: lxvx v3, 0, r4
+; CHECK-P9-NEXT: vperm v2, v2, v2, v3
+; CHECK-P9-NEXT: stxv vs0, 0(r3)
+; CHECK-P9-NEXT: vextsh2d v2, v2
+; CHECK-P9-NEXT: xvcvsxddp vs1, v2
+; CHECK-P9-NEXT: stxv vs1, 16(r3)
+; CHECK-P9-NEXT: blr
+;
+; CHECK-BE-LABEL: stest4:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: lxv v2, 0(r4)
+; CHECK-BE-NEXT: addis r4, r2, .LCPI4_0 at toc@ha
+; CHECK-BE-NEXT: xxlxor v3, v3, v3
+; CHECK-BE-NEXT: addi r4, r4, .LCPI4_0 at toc@l
+; CHECK-BE-NEXT: lxvx v4, 0, r4
+; CHECK-BE-NEXT: addis r4, r2, .LCPI4_1 at toc@ha
+; CHECK-BE-NEXT: addi r4, r4, .LCPI4_1 at toc@l
+; CHECK-BE-NEXT: vperm v3, v3, v2, v4
+; CHECK-BE-NEXT: vextsh2d v3, v3
+; CHECK-BE-NEXT: xvcvsxddp vs0, v3
+; CHECK-BE-NEXT: lxvx v3, 0, r4
+; CHECK-BE-NEXT: vperm v2, v2, v2, v3
+; CHECK-BE-NEXT: stxv vs0, 16(r3)
+; CHECK-BE-NEXT: vextsh2d v2, v2
+; CHECK-BE-NEXT: xvcvsxddp vs1, v2
+; CHECK-BE-NEXT: stxv vs1, 0(r3)
+; CHECK-BE-NEXT: blr
entry:
%0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16
%1 = sitofp <4 x i16> %0 to <4 x double>
store <4 x double> %1, <4 x double>* %Sink, align 16
ret void
-; CHECK-P9-LABEL: @stest4
-; CHECK-P9: vperm
-; CHECK-P9: vextsh2d
-; CHECK-P9: xvcvsxddp
-; CHECK-P9: vperm
-; CHECK-P9: vextsh2d
-; CHECK-P9: xvcvsxddp
}
define void @stest2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) {
+; CHECK-P8-LABEL: stest2:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0 at toc@ha
+; CHECK-P8-NEXT: lvx v3, 0, r4
+; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1 at toc@ha
+; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0 at toc@l
+; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1 at toc@l
+; CHECK-P8-NEXT: lvx v2, 0, r5
+; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
+; CHECK-P8-NEXT: vperm v2, v3, v3, v2
+; CHECK-P8-NEXT: xxswapd v3, vs0
+; CHECK-P8-NEXT: vsld v2, v2, v3
+; CHECK-P8-NEXT: vsrad v2, v2, v3
+; CHECK-P8-NEXT: xvcvsxddp vs0, v2
+; CHECK-P8-NEXT: xxswapd vs0, vs0
+; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
+; CHECK-P8-NEXT: blr
+;
+; CHECK-P9-LABEL: stest2:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: lxv v2, 0(r4)
+; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0 at toc@ha
+; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0 at toc@l
+; CHECK-P9-NEXT: lxvx v3, 0, r4
+; CHECK-P9-NEXT: vperm v2, v2, v2, v3
+; CHECK-P9-NEXT: vextsh2d v2, v2
+; CHECK-P9-NEXT: xvcvsxddp vs0, v2
+; CHECK-P9-NEXT: stxv vs0, 0(r3)
+; CHECK-P9-NEXT: blr
+;
+; CHECK-BE-LABEL: stest2:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: lxv v2, 0(r4)
+; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0 at toc@ha
+; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0 at toc@l
+; CHECK-BE-NEXT: lxvx v3, 0, r4
+; CHECK-BE-NEXT: vperm v2, v2, v2, v3
+; CHECK-BE-NEXT: vextsh2d v2, v2
+; CHECK-BE-NEXT: xvcvsxddp vs0, v2
+; CHECK-BE-NEXT: stxv vs0, 0(r3)
+; CHECK-BE-NEXT: blr
entry:
%0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16
%1 = sitofp <2 x i16> %0 to <2 x double>
store <2 x double> %1, <2 x double>* %Sink, align 16
ret void
-; CHECK-P9-LABEL: .LCPI5_0:
-; CHECK-P9-NEXT: .byte 31
-; CHECK-P9-NEXT: .byte 30
-; CHECK-P9-NEXT: .byte 31
-; CHECK-P9-NEXT: .byte 31
-; CHECK-P9-NEXT: .byte 31
-; CHECK-P9-NEXT: .byte 31
-; CHECK-P9-NEXT: .byte 31
-; CHECK-P9-NEXT: .byte 31
-; CHECK-P9-NEXT: .byte 29
-; CHECK-P9-NEXT: .byte 28
-; CHECK-P9-NEXT: .byte 31
-; CHECK-P9-NEXT: .byte 31
-; CHECK-P9-NEXT: .byte 31
-; CHECK-P9-NEXT: .byte 31
-; CHECK-P9-NEXT: .byte 31
-; CHECK-P9-NEXT: .byte 31
-; CHECK-P9: vperm [[REG1:v[0-9]+]]
-; CHECK-P9: vextsh2d [[REG2:v[0-9]+]], [[REG1]]
-; CHECK-P9: xvcvsxddp {{vs[0-9]+}}, [[REG2]]
-; CHECK-BE-LABEL: .LCPI5_0:
-; CHECK-BE-NEXT: .byte 0
-; CHECK-BE-NEXT: .byte 0
-; CHECK-BE-NEXT: .byte 0
-; CHECK-BE-NEXT: .byte 0
-; CHECK-BE-NEXT: .byte 0
-; CHECK-BE-NEXT: .byte 0
-; CHECK-BE-NEXT: .byte 0
-; CHECK-BE-NEXT: .byte 1
-; CHECK-BE-NEXT: .byte 0
-; CHECK-BE-NEXT: .byte 0
-; CHECK-BE-NEXT: .byte 0
-; CHECK-BE-NEXT: .byte 0
-; CHECK-BE-NEXT: .byte 0
-; CHECK-BE-NEXT: .byte 0
-; CHECK-BE-NEXT: .byte 2
-; CHECK-BE-NEXT: .byte 3
-; CHECK-BE: addi [[REG1:r[0-9]+]], {{r[0-9]+}}, .LCPI5_0 at toc@l
-; CHECK-BE: lxvx [[REG2:v[0-9]+]], 0, [[REG1]]
-; CHECK-BE: vperm [[REG3:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, [[REG2]]
-; CHECK-BE: vextsh2d [[REG4:v[0-9]+]], [[REG3]]
-; CHECK-BE: xvcvsxddp {{vs[0-9]+}}, [[REG4]]
}
diff --git a/llvm/test/CodeGen/PowerPC/vec-trunc2.ll b/llvm/test/CodeGen/PowerPC/vec-trunc2.ll
index 5eea2389d710..9824d9e99fde 100644
--- a/llvm/test/CodeGen/PowerPC/vec-trunc2.ll
+++ b/llvm/test/CodeGen/PowerPC/vec-trunc2.ll
@@ -6,8 +6,7 @@
; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE
-define dso_local <8 x i8> @test8x32(i32 %i1, i32 %i2, i32 %i3, i32 %i4,
- i32 %i5, i32 %i6, i32 %i7, i32 %i8) {
+define dso_local <8 x i8> @test8x32(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8) {
; CHECK-LABEL: test8x32:
; CHECK: # %bb.0:
; CHECK-NEXT: rldimi r3, r4, 32, 0
@@ -113,8 +112,7 @@ define dso_local <4 x i16> @test4x64(i64 %i1, i64 %i2, i64 %i3, i64 %i4) {
ret <4 x i16> %v2
}
-define dso_local <8 x i16> @test8x24(i32 %i1, i32 %i2, i32 %i3, i32 %i4,
- i32 %i5, i32 %i6, i32 %i7, i32 %i8) {
+define dso_local <8 x i16> @test8x24(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8) {
; CHECK-LABEL: test8x24:
; CHECK: # %bb.0:
; CHECK-NEXT: mtvsrd v2, r3
More information about the llvm-commits
mailing list