[PATCH] D89079: [AMDGPU] Fix mai hazard VALU to LD/ST

[Austin Kerbow via Phabricator via llvm-commits]

kerbowa updated this revision to Diff 297082.
kerbowa added a comment.

Wt -> Wr


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89079/new/

https://reviews.llvm.org/D89079

Files:
  llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  llvm/test/CodeGen/AMDGPU/mai-hazards.mir


Index: llvm/test/CodeGen/AMDGPU/mai-hazards.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/mai-hazards.mir
+++ llvm/test/CodeGen/AMDGPU/mai-hazards.mir
@@ -480,6 +480,20 @@
 ...
 ---
 
+# GCN-LABEL: name: valu_write_vgpr_accvgpr_write_load_1_and_3_depend
+# GCN:      V_MOV_B32
+# GCN-NEXT: V_ACCVGPR_WRITE_B32
+# GCN-NEXT: S_NOP 0
+# GCN-NEXT: FLAT_LOAD_DWORD
+name:            valu_write_vgpr_accvgpr_write_load_1_and_3_depend
+body:             |
+  bb.0:
+    $vgpr0 = V_MOV_B32_e32 1, implicit $exec
+    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr2, implicit $exec
+    $vgpr4 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
+...
+---
+
 # GCN-LABEL: name: valu_write_vgpr_accvgpr_read_load_2_and_3_depend
 # GCN:      V_MOV_B32
 # GCN-NEXT: V_ACCVGPR_READ_B32
Index: llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1368,7 +1368,7 @@
     Register Reg = Op.getReg();
 
     const int AccVgprReadLdStWaitStates = 2;
-    const int VALUWriteAccVgprReadLdStDepVALUWaitStates = 1;
+    const int VALUWriteAccVgprRdWrLdStDepVALUWaitStates = 1;
     const int MaxWaitStates = 2;
 
     int WaitStatesNeededForUse = AccVgprReadLdStWaitStates -
@@ -1378,8 +1378,9 @@
     if (WaitStatesNeeded == MaxWaitStates)
       return WaitStatesNeeded; // Early exit.
 
-    auto IsVALUAccVgprReadCheckFn = [Reg, this] (MachineInstr *MI) {
-      if (MI->getOpcode() != AMDGPU::V_ACCVGPR_READ_B32)
+    auto IsVALUAccVgprRdWrCheckFn = [Reg, this](MachineInstr *MI) {
+      if (MI->getOpcode() != AMDGPU::V_ACCVGPR_READ_B32 &&
+          MI->getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32)
         return false;
       auto IsVALUFn = [] (MachineInstr *MI) {
         return SIInstrInfo::isVALU(*MI) && !SIInstrInfo::isMAI(*MI);
@@ -1388,8 +1389,8 @@
              std::numeric_limits<int>::max();
     };
 
-    WaitStatesNeededForUse = VALUWriteAccVgprReadLdStDepVALUWaitStates -
-      getWaitStatesSince(IsVALUAccVgprReadCheckFn, MaxWaitStates);
+    WaitStatesNeededForUse = VALUWriteAccVgprRdWrLdStDepVALUWaitStates -
+      getWaitStatesSince(IsVALUAccVgprRdWrCheckFn, MaxWaitStates);
     WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
   }
 


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