[PATCH] D88750: [GlobalISel] Add G_VECREDUCE_* opcodes for vector reductions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added inline comments.
This revision is now accepted and ready to land.


================
Comment at: llvm/test/MachineVerifier/test_vector_reductions.mir:1
+#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
----------------
Missing space before RUN


================
Comment at: llvm/test/MachineVerifier/test_vector_reductions.mir:18-20
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
----------------
Don't need this


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88750/new/

https://reviews.llvm.org/D88750