[PATCH] D88750: [GlobalISel] Add G_VECREDUCE_* opcodes for vector reductions

[Amara Emerson via Phabricator via llvm-commits]

aemerson updated this revision to Diff 296802.
aemerson added a comment.

Rename the STRICT variants to SEQ, consistent with the rename of the SDAG nodes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88750/new/

https://reviews.llvm.org/D88750

Files:
  llvm/docs/GlobalISel/GenericOpcode.rst
  llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
  llvm/include/llvm/Support/TargetOpcodes.def
  llvm/include/llvm/Target/GenericOpcodes.td
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
  llvm/test/MachineVerifier/test_vector_reductions.mir

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