[PATCH] D88994: Fix the default alignment of i1 vectors.

[Eli Friedman via Phabricator via llvm-commits]

efriedma created this revision.
efriedma added reviewers: craig.topper, arsenm, sdesmalen, dmgreen, jholewinski, paulwalker-arm, RKSimon, cameron.mcinally.
Herald added subscribers: kerbowa, pengfei, hiraditya, tpr, nhaehnle, jvesely, qcolombet.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.
efriedma requested review of this revision.
Herald added a subscriber: wdng.

Currently, the default alignment is much larger than the actual size of the vector in memory.  Fix this to use a sane default.

For SVE, temporarily remove lowering of load/store operations for predicates with less than 16 elements. The layout the backend was assuming for SVE predicates with less than 16 elements doesn't agree with the datalayout. More work probably needs to be done here.

This change is, strictly speaking, not backwards-compatible at the bitcode level. But probably nobody is actually depending on that; i1 vectors in memory are rare, and the code that does use them probably ends up forcing the alignment to something sane anyway.  If we think this is a concern, I can restrict this to scalable vectors for now (where it's actually causing issues for me at the moment).

I did my best to update the regression tests, but I'm not completely sure I did it correctly for amdgpu and nvptx.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D88994

Files:
  llvm/lib/IR/DataLayout.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
  llvm/test/CodeGen/AArch64/spillfill-sve.ll
  llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
  llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
  llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
  llvm/test/CodeGen/NVPTX/param-load-store.ll
  llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
  llvm/test/CodeGen/Thumb2/mve-masked-load.ll
  llvm/test/CodeGen/Thumb2/mve-masked-store.ll
  llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
  llvm/test/CodeGen/X86/avx512-extract-subvector-load-store.ll
  llvm/test/CodeGen/X86/avx512-mask-op.ll
  llvm/test/CodeGen/X86/avx512-select.ll
  llvm/test/CodeGen/X86/bitcast-vector-bool.ll
  llvm/test/CodeGen/X86/load-local-v3i129.ll
  llvm/test/CodeGen/X86/pr41619.ll
  llvm/test/CodeGen/X86/vector-sext.ll
  llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/weird-type-accesses.ll
  llvm/test/Transforms/SROA/vector-promotion-different-size.ll

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