[PATCH] D88787: [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics.

Amara Emerson via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Oct 7 10:37:06 PDT 2020 

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG322d0afd875d: [llvm][mlir] Promote the experimental reduction intrinsics to be first class… (authored by aemerson).

Changed prior to commit:
  https://reviews.llvm.org/D88787?vs=296603&id=296735#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88787/new/

https://reviews.llvm.org/D88787

Files:
  llvm/docs/LangRef.rst
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/CodeGen/BasicTTIImpl.h
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/Analysis/ConstantFolding.cpp
  llvm/lib/CodeGen/ExpandReductions.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/IR/IRBuilder.cpp
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
  llvm/lib/Target/ARM/ARMTargetTransformInfo.h
  llvm/lib/Target/ARM/MVETailPredication.cpp
  llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
  llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
  llvm/test/Analysis/CostModel/AArch64/vector-reduce.ll
  llvm/test/Analysis/CostModel/ARM/reduce-add.ll
  llvm/test/Analysis/CostModel/ARM/reduce-smax.ll
  llvm/test/Analysis/CostModel/ARM/reduce-smin.ll
  llvm/test/Analysis/CostModel/ARM/reduce-umax.ll
  llvm/test/Analysis/CostModel/ARM/reduce-umin.ll
  llvm/test/Analysis/CostModel/X86/reduce-add.ll
  llvm/test/Analysis/CostModel/X86/reduce-and.ll
  llvm/test/Analysis/CostModel/X86/reduce-fmax.ll
  llvm/test/Analysis/CostModel/X86/reduce-fmin.ll
  llvm/test/Analysis/CostModel/X86/reduce-mul.ll
  llvm/test/Analysis/CostModel/X86/reduce-or.ll
  llvm/test/Analysis/CostModel/X86/reduce-smax.ll
  llvm/test/Analysis/CostModel/X86/reduce-smin.ll
  llvm/test/Analysis/CostModel/X86/reduce-umax.ll
  llvm/test/Analysis/CostModel/X86/reduce-umin.ll
  llvm/test/Analysis/CostModel/X86/reduce-xor.ll
  llvm/test/Assembler/invalid-vecreduce.ll
  llvm/test/Bitcode/upgrade-vecreduce-intrinsics.ll
  llvm/test/Bitcode/upgrade-vecreduce-intrinsics.ll.bc
  llvm/test/CodeGen/AArch64/aarch64-addv.ll
  llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
  llvm/test/CodeGen/AArch64/arm64-vabs.ll
  llvm/test/CodeGen/AArch64/neon-dot-product.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
  llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-bool.ll
  llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
  llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
  llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
  llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-fmul-legalization-strict.ll
  llvm/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll
  llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
  llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll
  llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
  llvm/test/CodeGen/ARM/vecreduce-fmax-legalization-soft-float.ll
  llvm/test/CodeGen/ARM/vecreduce-fmin-legalization-soft-float.ll
  llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-soft-float.ll
  llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll
  llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/invariant-qreg.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/nested.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-reduce.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tp-multiple-vpst.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredicated-max.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-reduce-mve-tail.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir
  llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
  llvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
  llvm/test/CodeGen/Thumb2/mve-vaddv.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-bit.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-fmul.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-mul.ll
  llvm/test/CodeGen/Thumb2/mve-vmaxv.ll
  llvm/test/CodeGen/X86/haddsub.ll
  llvm/test/CodeGen/X86/pr45378.ll
  llvm/test/CodeGen/X86/vector-reduce-add.ll
  llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
  llvm/test/CodeGen/X86/vector-reduce-and-cmp.ll
  llvm/test/CodeGen/X86/vector-reduce-and.ll
  llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll
  llvm/test/CodeGen/X86/vector-reduce-fadd.ll
  llvm/test/CodeGen/X86/vector-reduce-fmax-fmin-fast.ll
  llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
  llvm/test/CodeGen/X86/vector-reduce-fmax.ll
  llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll
  llvm/test/CodeGen/X86/vector-reduce-fmin.ll
  llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll
  llvm/test/CodeGen/X86/vector-reduce-fmul.ll
  llvm/test/CodeGen/X86/vector-reduce-mul.ll
  llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
  llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
  llvm/test/CodeGen/X86/vector-reduce-or.ll
  llvm/test/CodeGen/X86/vector-reduce-smax.ll
  llvm/test/CodeGen/X86/vector-reduce-smin.ll
  llvm/test/CodeGen/X86/vector-reduce-umax.ll
  llvm/test/CodeGen/X86/vector-reduce-umin.ll
  llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
  llvm/test/CodeGen/X86/vector-reduce-xor.ll
  llvm/test/Instrumentation/MemorySanitizer/experimental-reduce.ll
  llvm/test/Instrumentation/MemorySanitizer/reduce.ll
  llvm/test/Transforms/InstCombine/vector-reductions.ll
  llvm/test/Transforms/InstSimplify/ConstProp/vecreduce.ll
  llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
  llvm/test/Transforms/LoopVectorize/AArch64/reduction-small-size.ll
  llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll
  llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
  llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
  llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
  llvm/test/Transforms/LoopVectorize/ARM/tail-fold-multiple-icmps.ll
  llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
  llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
  llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
  llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
  llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
  llvm/test/Transforms/LoopVectorize/X86/pr42674.ll
  llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
  llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
  llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
  llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
  llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
  llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
  llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
  llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
  llvm/test/Transforms/SLPVectorizer/AArch64/gather-root.ll
  llvm/test/Transforms/SLPVectorizer/AArch64/horizontal.ll
  llvm/test/Transforms/SLPVectorizer/AArch64/transpose.ll
  llvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll
  llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll
  llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
  llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll
  llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
  llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
  llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
  llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
  llvm/test/Transforms/SLPVectorizer/X86/reassociated-loads.ll
  llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
  llvm/test/Transforms/SLPVectorizer/X86/reduction_loads.ll
  llvm/test/Transforms/SLPVectorizer/X86/reduction_unrolled.ll
  llvm/test/Transforms/SLPVectorizer/X86/remark_horcost.ll
  llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
  llvm/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll
  llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll
  llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
  llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
  llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll
  mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
  mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
  mlir/include/mlir/Dialect/Vector/VectorOps.td
  mlir/integration_test/Dialect/LLVMIR/CPU/test-vector-reductions-fp.mlir
  mlir/integration_test/Dialect/LLVMIR/CPU/test-vector-reductions-int.mlir
  mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
  mlir/test/Conversion/VectorToLLVM/vector-reduction-to-llvm.mlir
  mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
  mlir/test/Target/llvmir-intrinsics.mlir

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