[llvm] b426421 - [AMDGPU] Remove SIInstrInfo::calculateLDSSpillAddress
Sebastian Neubauer via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 6 09:45:35 PDT 2020
Author: Sebastian Neubauer
Date: 2020-10-06T18:45:22+02:00
New Revision: b4264210f2b24b8fb40247f34decd4e14174559e
URL: https://github.com/llvm/llvm-project/commit/b4264210f2b24b8fb40247f34decd4e14174559e
DIFF: https://github.com/llvm/llvm-project/commit/b4264210f2b24b8fb40247f34decd4e14174559e.diff
LOG: [AMDGPU] Remove SIInstrInfo::calculateLDSSpillAddress
This function does not seem to be used anymore.
Differential Revision: https://reviews.llvm.org/D88904
Added:
Modified:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index abf6869fee15..86eb594489a9 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1488,101 +1488,6 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
.addMemOperand(MMO);
}
-/// \param @Offset Offset in bytes of the FrameIndex being spilled
-unsigned SIInstrInfo::calculateLDSSpillAddress(
- MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg,
- unsigned FrameOffset, unsigned Size) const {
- MachineFunction *MF = MBB.getParent();
- SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
- const DebugLoc &DL = MBB.findDebugLoc(MI);
- unsigned WorkGroupSize = MFI->getMaxFlatWorkGroupSize();
- unsigned WavefrontSize = ST.getWavefrontSize();
-
- Register TIDReg = MFI->getTIDReg();
- if (!MFI->hasCalculatedTID()) {
- MachineBasicBlock &Entry = MBB.getParent()->front();
- MachineBasicBlock::iterator Insert = Entry.front();
- const DebugLoc &DL = Insert->getDebugLoc();
-
- TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass,
- *MF);
- if (TIDReg == AMDGPU::NoRegister)
- return TIDReg;
-
- if (!AMDGPU::isShader(MF->getFunction().getCallingConv()) &&
- WorkGroupSize > WavefrontSize) {
- Register TIDIGXReg =
- MFI->getPreloadedReg(AMDGPUFunctionArgInfo::WORKGROUP_ID_X);
- Register TIDIGYReg =
- MFI->getPreloadedReg(AMDGPUFunctionArgInfo::WORKGROUP_ID_Y);
- Register TIDIGZReg =
- MFI->getPreloadedReg(AMDGPUFunctionArgInfo::WORKGROUP_ID_Z);
- Register InputPtrReg =
- MFI->getPreloadedReg(AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
- for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
- if (!Entry.isLiveIn(Reg))
- Entry.addLiveIn(Reg);
- }
-
- RS->enterBasicBlock(Entry);
- // FIXME: Can we scavenge an SReg_64 and access the subregs?
- Register STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
- Register STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
- BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
- .addReg(InputPtrReg)
- .addImm(SI::KernelInputOffsets::NGROUPS_Z);
- BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
- .addReg(InputPtrReg)
- .addImm(SI::KernelInputOffsets::NGROUPS_Y);
-
- // NGROUPS.X * NGROUPS.Y
- BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
- .addReg(STmp1)
- .addReg(STmp0);
- // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
- BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
- .addReg(STmp1)
- .addReg(TIDIGXReg);
- // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
- BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
- .addReg(STmp0)
- .addReg(TIDIGYReg)
- .addReg(TIDReg);
- // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
- getAddNoCarry(Entry, Insert, DL, TIDReg)
- .addReg(TIDReg)
- .addReg(TIDIGZReg)
- .addImm(0); // clamp bit
- } else {
- // Get the wave id
- BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
- TIDReg)
- .addImm(-1)
- .addImm(0);
-
- BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
- TIDReg)
- .addImm(-1)
- .addReg(TIDReg);
- }
-
- BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
- TIDReg)
- .addImm(2)
- .addReg(TIDReg);
- MFI->setTIDReg(TIDReg);
- }
-
- // Add FrameIndex to LDS offset
- unsigned LDSOffset = MFI->getLDSSize() + (FrameOffset * WorkGroupSize);
- getAddNoCarry(MBB, MI, DL, TmpReg)
- .addImm(LDSOffset)
- .addReg(TIDReg)
- .addImm(0); // clamp bit
-
- return TmpReg;
-}
-
void SIInstrInfo::insertWaitStates(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
int Count) const {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 8ce41c4ba8b3..08bf3d27c74d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -201,10 +201,6 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
- unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI,
- RegScavenger *RS, unsigned TmpReg,
- unsigned Offset, unsigned Size) const;
-
void materializeImmediate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL,
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