[llvm] 5588dbc - [SystemZAsmParser] Treat VR128 separately in ParseDirectiveInsn().

[Jonas Paulsson via llvm-commits]

Author: Jonas Paulsson
Date: 2020-10-06T14:42:40+02:00
New Revision: 5588dbce73be2c86bf1701b2ebbce47239130296

URL: https://github.com/llvm/llvm-project/commit/5588dbce73be2c86bf1701b2ebbce47239130296
DIFF: https://github.com/llvm/llvm-project/commit/5588dbce73be2c86bf1701b2ebbce47239130296.diff

LOG: [SystemZAsmParser] Treat VR128 separately in ParseDirectiveInsn().

This patch makes the parser
  - reject higher vector registers (>=16) in operands where they should not
    be accepted.
  - accept higher integers (>=16) in vector register operands.

Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D88888

Added: 
    

Modified: 
    llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
    llvm/test/MC/SystemZ/directive-insn-vector.s
    llvm/test/MC/SystemZ/regs-bad.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index be96612383c7..8da460381783 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -635,18 +635,18 @@ static struct InsnMatchEntry InsnMatchTable[] = {
   { "ssf", SystemZ::InsnSSF, 4,
     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
   { "vri", SystemZ::InsnVRI, 6,
-    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
+    { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
   { "vrr", SystemZ::InsnVRR, 7,
-    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_U4Imm,
+    { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
       MCK_U4Imm } },
   { "vrs", SystemZ::InsnVRS, 5,
-    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_U4Imm } },
+    { MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm } },
   { "vrv", SystemZ::InsnVRV, 4,
-    { MCK_U48Imm, MCK_AnyReg, MCK_BDVAddr64Disp12, MCK_U4Imm } },
+    { MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm } },
   { "vrx", SystemZ::InsnVRX, 4,
-    { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12, MCK_U4Imm } },
+    { MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm } },
   { "vsi", SystemZ::InsnVSI, 4,
-    { MCK_U48Imm, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_U8Imm } }
+    { MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm } }
 };
 
 static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
@@ -851,10 +851,11 @@ SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) {
 // Parse any type of register (including integers) and add it to Operands.
 OperandMatchResultTy
 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
+  SMLoc StartLoc = Parser.getTok().getLoc();
+
   // Handle integer values.
   if (Parser.getTok().is(AsmToken::Integer)) {
     const MCExpr *Register;
-    SMLoc StartLoc = Parser.getTok().getLoc();
     if (Parser.parseExpression(Register))
       return MatchOperand_ParseFail;
 
@@ -876,6 +877,11 @@ SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
     if (parseRegister(Reg))
       return MatchOperand_ParseFail;
 
+    if (Reg.Num > 15) {
+      Error(StartLoc, "invalid register");
+      return MatchOperand_ParseFail;
+    }
+
     // Map to the correct register kind.
     RegisterKind Kind;
     unsigned RegNo;
@@ -1208,6 +1214,8 @@ bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
     OperandMatchResultTy ResTy;
     if (Kind == MCK_AnyReg)
       ResTy = parseAnyReg(Operands);
+    else if (Kind == MCK_VR128)
+      ResTy = parseVR128(Operands);
     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
       ResTy = parseBDXAddr64(Operands);
     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)

diff  --git a/llvm/test/MC/SystemZ/directive-insn-vector.s b/llvm/test/MC/SystemZ/directive-insn-vector.s
index 04c53a8bbf85..9d4a7c6a6f87 100644
--- a/llvm/test/MC/SystemZ/directive-insn-vector.s
+++ b/llvm/test/MC/SystemZ/directive-insn-vector.s
@@ -25,3 +25,5 @@
 #CHECK: e6 0c 20 0c 01 35     vlrl    %v16, 12(%r2), 12
   .insn vsi,0xe60000000035,%v16,12(%r2),12
 
+#CHECK: e7 01 00 00 0c 56     vlr     %v16, %v17
+ .insn vrr,0xe70000000056,16,17,0,0,0,0

diff  --git a/llvm/test/MC/SystemZ/regs-bad.s b/llvm/test/MC/SystemZ/regs-bad.s
index db56af96638b..320cba0fc856 100644
--- a/llvm/test/MC/SystemZ/regs-bad.s
+++ b/llvm/test/MC/SystemZ/regs-bad.s
@@ -217,6 +217,13 @@
 	lxr	%f0,16
 	lxr	%f0,0(%r1)
 
+# Test that a high (>=16) vector register is not accepted in a non-vector
+# operand.
+#
+#CHECK: error: invalid register
+#CHECK: .insn rr,0x1800,%v16,%v0
+.insn rr,0x1800,%v16,%v0
+
 # Test access register operands
 #
 #CHECK: error: invalid operand for instruction