[PATCH] D88888: [SystemZAsmParser] Treat VR128 separately in ParseDirectiveInsn().

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa created this revision.
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Since vector registers require an extra bit of encoding they should not be part of the AnyReg register class together with the GPR and FP registers, so they are removed.

This patch makes the parser

- reject higher vector registers (>=16) in operands where they should not be accepted.
- accept higher integers (>=16) in vector register operands.


https://reviews.llvm.org/D88888

Files:
  llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
  llvm/lib/Target/SystemZ/SystemZRegisterInfo.td
  llvm/test/MC/SystemZ/directive-insn-vector.s
  llvm/test/MC/SystemZ/regs-bad.s

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