[PATCH] D88759: [RISCV] Add SiFive cores to the CPU option

[Evandro Menezes via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG5d6d8a2769b3: [RISCV] Add SiFive cores to the CPU option (authored by evandro).
Herald added subscribers: cfe-commits, jrtc27.
Herald added a project: clang.

Changed prior to commit:
  https://reviews.llvm.org/D88759?vs=295917&id=296290#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88759/new/

https://reviews.llvm.org/D88759

Files:
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D88759.296290.patch
Type: text/x-patch
Size: 6107 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20201005/46ebe0e3/attachment.bin>