[PATCH] D87705: [PowerPC] Implement Set Boolean Condition Instructions

[Victor Huang via Phabricator via llvm-commits]

NeHuang added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/p10-spill-creq.ll:4
+; RUN:     -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:     FileCheck %s
+
----------------
Use `--check-prefix=CHECK-P10` here?


================
Comment at: llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll:4
+; RUN:     -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:     FileCheck %s
+
----------------
Use `--check-prefix=CHECK-P10` here?


================
Comment at: llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll:4
+; RUN:     -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:     FileCheck %s
+
----------------
Use `--check-prefix=CHECK-P10` here to be consistent with other IR cases


================
Comment at: llvm/test/CodeGen/PowerPC/p10-spill-crun.ll:4
+; RUN:     -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:     FileCheck %s
+
----------------
Use `--check-prefix=CHECK-P10` here to be consistent with other IR cases?


================
Comment at: llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll:72
+; CHECK-P10:         cmplw r4, r3
+; CHECK-P10-NEXT:    setbc r3, gt
 entry:
----------------
Are we missing the instructions check between `setbcr3, gt` and blr?


================
Comment at: llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll:72
+; CHECK-P10:         cmplw r4, r3
+; CHECK-P10-NEXT:    setbc r3, lt
 entry:
----------------
Are we missing the instructions check between `setbcr3, lt` and `blr`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87705/new/

https://reviews.llvm.org/D87705