[PATCH] D88256: [NFC][regalloc] Separate iteration from AllocationOrder
Quentin Colombet via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 5 11:36:22 PDT 2020
qcolombet accepted this revision.
qcolombet added a comment.
This revision is now accepted and ready to land.
LGTM with nitpicks
================
Comment at: llvm/lib/CodeGen/RegAllocGreedy.cpp:811
Register PhysReg;
- while ((PhysReg = Order.next())) {
- if (PhysReg == PrevReg)
+ for (auto I = Order.begin(), E = Order.end(); I != E && !PhysReg; ++I) {
+ if (*I == PrevReg)
----------------
Could we just stick to assigning PhysReg at the beginning of the loop?
That way we don't have to modify the body of the loop.
================
Comment at: llvm/lib/CodeGen/RegAllocGreedy.cpp:1860
unsigned BestCand = NoCand;
- Order.rewind();
- while (unsigned PhysReg = Order.next()) {
+ for (auto PhysReg : Order) {
+ assert(PhysReg);
----------------
Could you call out the type here?
Put differently, I don't like the use of `auto` when the type is not immediately obvious.
================
Comment at: llvm/lib/CodeGen/RegAllocGreedy.cpp:2299
- Order.rewind();
- while (unsigned PhysReg = Order.next()) {
+ for (auto PhysReg : Order) {
+ assert(PhysReg);
----------------
Ditto with the use of `auto`
================
Comment at: llvm/lib/CodeGen/RegAllocGreedy.cpp:2617
- Order.rewind();
- while (Register PhysReg = Order.next()) {
+ for (auto PhysReg : Order) {
+ assert(PhysReg);
----------------
Ditto with the use of `auto`
Repository:
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https://reviews.llvm.org/D88256/new/
https://reviews.llvm.org/D88256
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