[PATCH] D88791: Rename the VECREDUCE_STRICT_{FADD,FMUL} SDNodes to VECREDUCE_SEQ_{FADD,FMUL}.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/include/llvm/CodeGen/ISDOpcodes.h:1108
   /// operand is an initial scalar accumulator value, and the second operand
   /// is the vector to reduce.
+  VECREDUCE_SEQ_FADD,
----------------
aemerson wrote:
> RKSimon wrote:
> > To avoid ambiguity - please can you add a codesnippet to the comment showing the order? Maybe something similar to relaxed variants below showing possible expansions (and maybe what the default legalizing expansion is?).
> Sure, will do.
Shouldn't that be:
```
RES = VECREDUCE_SEQ_FADD float ACC, <4 x float> SRC_VEC
```


================
Comment at: llvm/include/llvm/CodeGen/ISDOpcodes.h:1111
+  VECREDUCE_SEQ_FMUL,
   /// These reductions are non-strict, and have a single vector operand.
   VECREDUCE_FADD,
----------------
dmgreen wrote:
> -> These reductions are not strictly ordered, ...
Check types - FADD or ADD ?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88791/new/

https://reviews.llvm.org/D88791