[PATCH] D88742: [AArch64] Identify SAD pattern for v16i8 type

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

So this converts `v16i32 abs(sub(zext(v16i8), zext(v16i8))))` to `v16i32 zext(abd(v16i8, v16i8))`? And doesn't start with a trunk? That sounds like it should work OK.

Can you add other types and sign extends? And more tests. And a AArch64ISD node (they are not very complex to add :) )


Repository:
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https://reviews.llvm.org/D88742