[PATCH] D88629: [lld-macho] Add ARM64 target arch

[Jez Ng via Phabricator via llvm-commits]

int3 added inline comments.


================
Comment at: lld/MachO/Arch/ARM64.cpp:48
+  RelocationInfoType type;
+  llvm::Optional<bool> TLV;
+  bool PCrel;
----------------
What's the difference between `None` and `false` here?

(Also, clang-tidy naming issues seem legit)


================
Comment at: lld/MachO/Arch/ARM64.cpp:79-90
+  switch (rel.r_length) {
+  case 0:
+    return *loc;
+  case 1:
+    return read16le(loc);
+  case 2:
+    return read32le(loc);
----------------
can we factor this out and reuse it across both architectures?


================
Comment at: lld/MachO/Arch/ARM64.cpp:93-107
+inline uint64_t bitField(uint64_t value, int right, int width, int left) {
+  return ((value >> right) & ((1 << width) - 1)) << left;
+}
+
+inline uint64_t fixupBranch26(uint64_t encoding, uint64_t va) {
+  return (encoding | bitField(va, 2, 26, 0));
+}
----------------
some comments about the different arm64 instruction formats would be helpful


================
Comment at: lld/MachO/Arch/X86_64.cpp:125
+void X86_64::relocateOne(uint8_t *loc, const Reloc &r, uint64_t va) const {
+  // For instruction fixups, r.addend contains the base encoding
+  va += r.addend;
----------------
what does 'base encoding' mean?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88629/new/

https://reviews.llvm.org/D88629