[PATCH] D88750: [GlobalISel] Add G_VECREDUCE_* opcodes for vector reductions

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added reviewers: arsenm, paquette, foad, dsanders, aditya_nandakumar, qcolombet, volkan.
aemerson added a project: LLVM.
Herald added subscribers: hiraditya, rovka.
aemerson requested review of this revision.
Herald added a subscriber: wdng.

These mirror the IR and SelectionDAG intrinsics & nodes.

Opcodes added:
G_VECREDUCE_STRICT_FADD
G_VECREDUCE_STRICT_FMUL
G_VECREDUCE_FADD
G_VECREDUCE_FMUL
G_VECREDUCE_FMAX
G_VECREDUCE_FMIN
G_VECREDUCE_ADD
G_VECREDUCE_MUL
G_VECREDUCE_AND
G_VECREDUCE_OR
G_VECREDUCE_XOR
G_VECREDUCE_SMAX
G_VECREDUCE_SMIN
G_VECREDUCE_UMAX
G_VECREDUCE_UMIN


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D88750

Files:
  llvm/docs/GlobalISel/GenericOpcode.rst
  llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
  llvm/include/llvm/Support/TargetOpcodes.def
  llvm/include/llvm/Target/GenericOpcodes.td
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
  llvm/test/MachineVerifier/test_vector_reductions.mir

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