[llvm] 017b871 - [AArch64][GlobalISel] Alias rules for G_FCMP to G_ICMP.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 1 15:20:31 PDT 2020
Author: Amara Emerson
Date: 2020-10-01T15:20:09-07:00
New Revision: 017b871502b0c6fe72f52c5b47780f77e38d9035
URL: https://github.com/llvm/llvm-project/commit/017b871502b0c6fe72f52c5b47780f77e38d9035
DIFF: https://github.com/llvm/llvm-project/commit/017b871502b0c6fe72f52c5b47780f77e38d9035.diff
LOG: [AArch64][GlobalISel] Alias rules for G_FCMP to G_ICMP.
No need to be different here for the vast majority of rules.
Added:
llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-cmp.mir
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
Removed:
llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-icmp.mir
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 182727cd062f..4da8406f3569 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -326,8 +326,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.legalFor({s32, s64})
.clampScalar(0, s32, s64);
-
- getActionDefinitionsBuilder(G_ICMP)
+
+ getActionDefinitionsBuilder({G_ICMP, G_FCMP})
.legalFor({{s32, s32},
{s32, s64},
{s32, p0},
@@ -358,12 +358,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.widenScalarOrEltToNextPow2(1)
.clampNumElements(0, v2s32, v4s32);
- getActionDefinitionsBuilder(G_FCMP)
- .legalFor({{s32, s32}, {s32, s64}})
- .clampScalar(0, s32, s32)
- .clampScalar(1, s32, s64)
- .widenScalarToNextPow2(1);
-
// Extensions
auto ExtLegalFunc = [=](const LegalityQuery &Query) {
unsigned DstSize = Query.Types[0].getSizeInBits();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-icmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-cmp.mir
similarity index 93%
rename from llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-icmp.mir
rename to llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-cmp.mir
index ec0446d0236f..3ec41a3a9358 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-icmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-cmp.mir
@@ -1996,3 +1996,109 @@ body: |
$d0 = COPY %7(<8 x s8>)
RET_ReallyLR implicit $d0
...
+---
+name: fcmp_8xs1
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$q0' }
+ - { reg: '$q1' }
+ - { reg: '$q2' }
+ - { reg: '$q3' }
+body: |
+ bb.1:
+ liveins: $q0, $q1, $q2, $q3
+
+ ; CHECK-LABEL: name: fcmp_8xs1
+ ; CHECK: liveins: $q0, $q1, $q2, $q3
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
+ ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
+ ; CHECK: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3
+ ; CHECK: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(one), [[COPY]](<4 x s32>), [[COPY2]]
+ ; CHECK: [[FCMP1:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(one), [[COPY1]](<4 x s32>), [[COPY3]]
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP1]](<4 x s32>)
+ ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)
+ ; CHECK: $d0 = COPY [[TRUNC2]](<8 x s8>)
+ ; CHECK: RET_ReallyLR implicit $d0
+ %2:_(<4 x s32>) = COPY $q0
+ %3:_(<4 x s32>) = COPY $q1
+ %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>)
+ %4:_(<4 x s32>) = COPY $q2
+ %5:_(<4 x s32>) = COPY $q3
+ %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>)
+ %6:_(<8 x s1>) = G_FCMP floatpred(one), %0(<8 x s32>), %1
+ %7:_(<8 x s8>) = G_ANYEXT %6(<8 x s1>)
+ $d0 = COPY %7(<8 x s8>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: fcmp_8xs32
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$q0' }
+ - { reg: '$q1' }
+ - { reg: '$q2' }
+ - { reg: '$q3' }
+body: |
+ bb.1:
+ liveins: $q0, $q1, $q2, $q3
+
+ ; CHECK-LABEL: name: fcmp_8xs32
+ ; CHECK: liveins: $q0, $q1, $q2, $q3
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
+ ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
+ ; CHECK: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3
+ ; CHECK: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(oeq), [[COPY]](<4 x s32>), [[COPY2]]
+ ; CHECK: [[FCMP1:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(oeq), [[COPY1]](<4 x s32>), [[COPY3]]
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP1]](<4 x s32>)
+ ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)
+ ; CHECK: $d0 = COPY [[TRUNC2]](<8 x s8>)
+ ; CHECK: RET_ReallyLR implicit $d0
+ %2:_(<4 x s32>) = COPY $q0
+ %3:_(<4 x s32>) = COPY $q1
+ %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>)
+ %4:_(<4 x s32>) = COPY $q2
+ %5:_(<4 x s32>) = COPY $q3
+ %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>)
+ %6:_(<8 x s32>) = G_FCMP floatpred(oeq), %0(<8 x s32>), %1
+ %7:_(<8 x s8>) = G_TRUNC %6(<8 x s32>)
+ $d0 = COPY %7(<8 x s8>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: fcmp_v4s32
+alignment: 4
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+ - { id: 3, class: _ }
+machineFunctionInfo: {}
+body: |
+ bb.1:
+ liveins: $q0, $q1
+
+ ; CHECK-LABEL: name: fcmp_v4s32
+ ; CHECK: liveins: $q0, $q1
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
+ ; CHECK: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(olt), [[COPY]](<4 x s32>), [[COPY1]]
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>)
+ ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>)
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:_(<4 x s32>) = COPY $q0
+ %1:_(<4 x s32>) = COPY $q1
+ %2:_(<4 x s1>) = G_FCMP floatpred(olt), %0(<4 x s32>), %1
+ %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
+ $d0 = COPY %3(<4 x s16>)
+ RET_ReallyLR implicit $d0
+
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 357eb8b981c5..4d49365a8dab 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -286,8 +286,9 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_FCMP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. the first uncovered type index: 2, OK
-# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_SELECT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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