[llvm] e28c589 - [AArch64][GlobalISel] Make <8 x s8> integer arithmetic ops legal.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2020-10-01T14:35:21-07:00
New Revision: e28c5899a24117cdb0b081a54508af486a2634a0

URL: https://github.com/llvm/llvm-project/commit/e28c5899a24117cdb0b081a54508af486a2634a0
DIFF: https://github.com/llvm/llvm-project/commit/e28c5899a24117cdb0b081a54508af486a2634a0.diff

LOG: [AArch64][GlobalISel] Make <8 x s8> integer arithmetic ops legal.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
    llvm/test/CodeGen/AArch64/arm64-vabs.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 8e38880034c3..182727cd062f 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -100,7 +100,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .widenScalarToNextPow2(0);
 
   getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
-      .legalFor({s32, s64, v2s32, v4s32, v4s16, v8s16, v16s8})
+      .legalFor({s32, s64, v2s32, v4s32, v4s16, v8s16, v16s8, v8s8})
       .scalarizeIf(
           [=](const LegalityQuery &Query) {
             return Query.Opcode == G_MUL && Query.Types[0] == v2s64;

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
index 5e0755836ce4..ab8510bf9d92 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
@@ -194,3 +194,23 @@ body:             |
     $d0 = COPY %2(<4 x s16>)
     RET_ReallyLR implicit $d0
 ...
+---
+name:            add_v8s8
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $d0, $d1
+
+    ; CHECK-LABEL: name: add_v8s8
+    ; CHECK: liveins: $d0, $d1
+    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+    ; CHECK: [[ADD:%[0-9]+]]:_(<8 x s8>) = G_ADD [[COPY]], [[COPY1]]
+    ; CHECK: $d0 = COPY [[ADD]](<8 x s8>)
+    ; CHECK: RET_ReallyLR implicit $d0
+    %0:_(<8 x s8>) = COPY $d0
+    %1:_(<8 x s8>) = COPY $d1
+    %2:_(<8 x s8>) = G_ADD %0, %1
+    $d0 = COPY %2(<8 x s8>)
+    RET_ReallyLR implicit $d0
+...

diff  --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index 636522901ba4..419cafc23186 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -982,8 +982,12 @@ define <4 x i16> @abspattern2(<4 x i16> %a) nounwind {
 
 define <8 x i8> @abspattern3(<8 x i8> %a) nounwind {
 ; CHECK-LABEL: abspattern3:
-; CHECK: abs.8b
-; CHECK-NEXT: ret
+; DAG: abs.8b
+; DAG-NEXT: ret
+
+; GISEL-DAG: neg.8b
+; GISEL-DAG: cmgt.8b
+; GISEL: bit.8b
         %tmp1neg = sub <8 x i8> zeroinitializer, %a
         %b = icmp slt <8 x i8> %a, zeroinitializer
         %abs = select <8 x i1> %b, <8 x i8> %tmp1neg, <8 x i8> %a