[llvm] 48c9e82 - [ARM] Removed hasSideEffects from signed/unsigned saturates

[Meera Nakrani via llvm-commits]

Author: Meera Nakrani
Date: 2020-10-01T14:55:01Z
New Revision: 48c9e8244b6b8aeb6a4fd10dcf4c6995f1fec9a0

URL: https://github.com/llvm/llvm-project/commit/48c9e8244b6b8aeb6a4fd10dcf4c6995f1fec9a0
DIFF: https://github.com/llvm/llvm-project/commit/48c9e8244b6b8aeb6a4fd10dcf4c6995f1fec9a0.diff

LOG: [ARM] Removed hasSideEffects from signed/unsigned saturates

Removed hasSideEffects from SSAT and USAT so that they are no longer
marked as unpredictable.

Differential Revision: https://reviews.llvm.org/D88545

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMInstrThumb2.td
    llvm/test/tools/llvm-mca/ARM/m4-int.s

Removed: 
    


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diff  --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 3aea1925a380..74627b0c1cdc 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -2575,7 +2575,6 @@ def t2USADA8  : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
           Requires<[IsThumb2, HasDSP]>;
 
 // Signed/Unsigned saturate.
-let hasSideEffects = 1 in
 class T2SatI<dag iops, string opc, string asm>
   : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, []> {
   bits<4> Rd;

diff  --git a/llvm/test/tools/llvm-mca/ARM/m4-int.s b/llvm/test/tools/llvm-mca/ARM/m4-int.s
index b46f731f0793..c2468efea205 100644
--- a/llvm/test/tools/llvm-mca/ARM/m4-int.s
+++ b/llvm/test/tools/llvm-mca/ARM/m4-int.s
@@ -746,9 +746,9 @@ yield
 # CHECK-NEXT:  1      1     1.00                        smulwt	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        smusd	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        smusdx	r0, r1, r2
-# CHECK-NEXT:  1      1     1.00                  U     ssat	r0, #1, r2
-# CHECK-NEXT:  1      1     1.00                  U     ssat	r0, #1, r2, lsl #1
-# CHECK-NEXT:  1      1     1.00                  U     ssat16	r0, #1, r1
+# CHECK-NEXT:  1      1     1.00                        ssat	r0, #1, r2
+# CHECK-NEXT:  1      1     1.00                        ssat	r0, #1, r2, lsl #1
+# CHECK-NEXT:  1      1     1.00                        ssat16	r0, #1, r1
 # CHECK-NEXT:  1      1     1.00    *      *      U     ssax	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00    *      *      U     ssbb
 # CHECK-NEXT:  1      1     1.00    *      *      U     ssub16	r0, r1, r2
@@ -858,9 +858,9 @@ yield
 # CHECK-NEXT:  1      1     1.00                        uqsub8	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        usad8	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        usada8	r0, r1, r2, r3
-# CHECK-NEXT:  1      1     1.00                  U     usat	r0, #1, r1
-# CHECK-NEXT:  1      1     1.00                  U     usat	r0, #1, r1, lsl #1
-# CHECK-NEXT:  1      1     1.00                  U     usat16	r0, #1, r1
+# CHECK-NEXT:  1      1     1.00                        usat	r0, #1, r1
+# CHECK-NEXT:  1      1     1.00                        usat	r0, #1, r1, lsl #1
+# CHECK-NEXT:  1      1     1.00                        usat16	r0, #1, r1
 # CHECK-NEXT:  1      1     1.00    *      *      U     usax	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00    *      *      U     usub16	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00    *      *      U     usub8	r0, r1, r2