[PATCH] D88577: [AArch64] Generate udot for v16i8 sum reduction to i32
Sjoerd Meijer via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 1 02:29:49 PDT 2020
SjoerdMeijer added a comment.
I haven't looked in much detail at this patch, but this looks like some straightforward lowering of `llvm.experimental.vector.reduce.add`. Absolutely nothing wrong with that, but I am curious who's going to produce this intrinsic? The vectoriser, the matrix pass? In other words, any ideas on the bigger picture?
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D88577/new/
https://reviews.llvm.org/D88577
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