[llvm] 93a1fc2 - Try to fix build. May have used a C++ feature too new/not supported on all platforms.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2020-09-30T17:36:38-07:00
New Revision: 93a1fc2e18b452216be70f534da42f7702adbe1d

URL: https://github.com/llvm/llvm-project/commit/93a1fc2e18b452216be70f534da42f7702adbe1d
DIFF: https://github.com/llvm/llvm-project/commit/93a1fc2e18b452216be70f534da42f7702adbe1d.diff

LOG: Try to fix build. May have used a C++ feature too new/not supported on all platforms.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 206e40999224..b6a006eba53b 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -23,6 +23,7 @@
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/Type.h"
+#include <initializer_list>
 
 #define DEBUG_TYPE "aarch64-legalinfo"
 
@@ -54,11 +55,12 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
   const LLT v2s64 = LLT::vector(2, 64);
   const LLT v2p0 = LLT::vector(2, p0);
 
-  const auto PackedVectorAllTypeList = {/* Begin 128bit types */
-                                        v16s8, v8s16, v4s32, v2s64, v2p0,
-                                        /* End 128bit types */
-                                        /* Begin 64bit types */
-                                        v8s8, v4s16, v2s32};
+  std::initializer_list<LLT> PackedVectorAllTypeList = {/* Begin 128bit types */
+                                                        v16s8, v8s16, v4s32,
+                                                        v2s64, v2p0,
+                                                        /* End 128bit types */
+                                                        /* Begin 64bit types */
+                                                        v8s8, v4s16, v2s32};
 
   const TargetMachine &TM = ST.getTargetLowering()->getTargetMachine();