[PATCH] D88569: [DAGCombiner] Call SimplifyDemandedBits to simplify EXTRACT_VECTOR_ELT

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added reviewers: RKSimon, nikic, craig.topper, spatel.
Herald added subscribers: llvm-commits, ecnelises, kerbowa, dmgreen, atanasyan, jrtc27, hiraditya, nhaehnle, jvesely, nemanjai, sdardis.
Herald added a project: LLVM.
foad requested review of this revision.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D88569

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/arm64-build-vector.ll
  llvm/test/CodeGen/AArch64/dag-numsignbits.ll
  llvm/test/CodeGen/AArch64/popcount.ll
  llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
  llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/usub_sat_vec.ll
  llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
  llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
  llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
  llvm/test/CodeGen/AMDGPU/saddsat.ll
  llvm/test/CodeGen/AMDGPU/sdiv64.ll
  llvm/test/CodeGen/AMDGPU/shift-i128.ll
  llvm/test/CodeGen/AMDGPU/srem64.ll
  llvm/test/CodeGen/AMDGPU/ssubsat.ll
  llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
  llvm/test/CodeGen/AMDGPU/uaddsat.ll
  llvm/test/CodeGen/AMDGPU/usubsat.ll
  llvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
  llvm/test/CodeGen/ARM/fp16-insert-extract.ll
  llvm/test/CodeGen/ARM/vdup.ll
  llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
  llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll
  llvm/test/CodeGen/ARM/vldlane.ll
  llvm/test/CodeGen/ARM/vzip.ll
  llvm/test/CodeGen/Mips/cconv/vector.ll
  llvm/test/CodeGen/PowerPC/pr45709.ll
  llvm/test/CodeGen/Thumb2/active_lane_mask.ll
  llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
  llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll
  llvm/test/CodeGen/Thumb2/mve-shuffle.ll
  llvm/test/CodeGen/Thumb2/mve-soft-float-abi.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
  llvm/test/CodeGen/Thumb2/mve-vld2-post.ll
  llvm/test/CodeGen/Thumb2/mve-vld2.ll
  llvm/test/CodeGen/Thumb2/mve-vld3.ll
  llvm/test/CodeGen/Thumb2/mve-vld4-post.ll
  llvm/test/CodeGen/Thumb2/mve-vld4.ll
  llvm/test/CodeGen/Thumb2/mve-vldst4.ll
  llvm/test/CodeGen/Thumb2/mve-vmulh.ll
  llvm/test/CodeGen/Thumb2/mve-vmull-loop.ll
  llvm/test/CodeGen/Thumb2/mve-vqmovn.ll
  llvm/test/CodeGen/Thumb2/mve-vqshrn.ll
  llvm/test/CodeGen/Thumb2/mve-vst2.ll
  llvm/test/CodeGen/Thumb2/mve-vst3.ll
  llvm/test/CodeGen/Thumb2/mve-vst4.ll
  llvm/test/CodeGen/Thumb2/mve-zext-masked-load.ll
  llvm/test/CodeGen/X86/bitcast-vector-bool.ll
  llvm/test/CodeGen/X86/buildvec-insertvec.ll
  llvm/test/CodeGen/X86/madd.ll
  llvm/test/CodeGen/X86/promote-cmp.ll
  llvm/test/CodeGen/X86/vec_setcc.ll
  llvm/test/CodeGen/X86/vector-fshl-128.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshr-128.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
  llvm/test/CodeGen/X86/vector-reduce-mul.ll
  llvm/test/CodeGen/X86/vector-trunc-math.ll
  llvm/test/CodeGen/X86/vselect.ll

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