[PATCH] D87236: [X86][SSE2] Use smarter instruction patterns for lowering UMIN/UMAX with v8i16 and SMIN/SMAX with v16i8.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:26771
+                         DAG.getNode(ISD::USUBSAT, DL, VT, N0, N1));
+    }
+    return DAG.getNode(ISD::ADD, DL, VT,
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(style) Remove braces


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Comment at: llvm/test/CodeGen/X86/vselect-minmax.ll:16
+; SSE2-NEXT:    pminub %xmm1, %xmm0
+; SSE2-NEXT:    pxor %xmm2, %xmm0
 ; SSE2-NEXT:    retq
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Regressions? Increased instruction count (the movdqa rr on the other side is effectively free) + constant pool load.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87236/new/

https://reviews.llvm.org/D87236