[PATCH] D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll:69
+; CHECK-LABEL: fmaxv_v64f16:
+; VBITS_GE_1048: ptrue [[PG:p[0-9]+]].h, vl64
+; VBITS_GE_1048-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
----------------
1024


================
Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll:131
+; CHECK-LABEL: fmaxv_v32f32:
+; VBITS_GE_1048: ptrue [[PG:p[0-9]+]].s, vl32
+; VBITS_GE_1048-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
----------------
1024


================
Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll:142
+; CHECK-LABEL: fmaxv_v64f32:
+; VBITS_GE_2096: ptrue [[PG:p[0-9]+]].s, vl64
+; VBITS_GE_2096-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
----------------
2048


================
Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll:259
+; CHECK-LABEL: fminv_v64f16:
+; VBITS_GE_1048: ptrue [[PG:p[0-9]+]].h, vl64
+; VBITS_GE_1048-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
----------------
1024


================
Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll:322
+; VBITS_GE_1048: ptrue [[PG:p[0-9]+]].s, vl32
+; VBITS_GE_1048-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_1048-NEXT: fminnmv s0, [[PG]], [[OP]].s
----------------
1024


================
Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll:333
+; VBITS_GE_2096: ptrue [[PG:p[0-9]+]].s, vl64
+; VBITS_GE_2096-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_2096-NEXT: fminnmv s0, [[PG]], [[OP]].s
----------------
2048


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88444/new/

https://reviews.llvm.org/D88444