[PATCH] D88315: [AMDGPU] Do not generate mul with 1 in AMDGPU Atomic Optimizer

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 29 07:22:53 PDT 2020


arsenm added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll:7-10
+; GCN-NOT: s_mul_i32 s[[REG1:[0-9]+]], s[[REG2:[0-9]+]], 1
+; GCN-NOT: s_mul_i32 s[[REG1:[0-9]+]], 1, s[[REG2:[0-9]+]]
+; GCN-NOT: v_mul_lo_u32 v[[REG1:[0-9]+]], v[[REG2:[0-9]+]], 1
+; GCN-NOT: v_mul_lo_u32 v[[REG1:[0-9]+]], 1, v[[REG2:[0-9]+]]
----------------
mbrkusanin wrote:
> arsenm wrote:
> > These negative checks are extremely fragile. These should use positive checks
> Just llc or opt check lines as well?
Both. Negative checks are just too easy to get wrong


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88315/new/

https://reviews.llvm.org/D88315



More information about the llvm-commits mailing list