[PATCH] D88214: [TableGen] Added a function to identify unsupported opcodes

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

Hi @dp, I believe that I encountered the same issue when adding the assembler support for AArch64 SVE.

In D40363 <https://reviews.llvm.org/D40363> I added a `bool ParseForAllFeatures` to `MatchOperandParserImpl`. By passing `true` for this parameter, the assembler will continue trying to match the operands regardless of which feature bits are set. `MatchInstructionImpl` (generated by TableGen) will finally check if the parsed mnemonic + operands combination is valid using the AsmOperand's predicate methods and the selected FeatureSet. It will emit a suitable diagnostic if the operand is not valid. If the operands are all valid but the instruction is not in the feature set, it will return `Match_MissingFeature`.

A limitation of `emitMnemonicChecker` you added here is that it doesn't work for different instructions with the same mnemonic. For example some arch-features might enable additional addressing modes, or enable instructions with the same mnemonic, but with different registers (e.g. Neon vs SVE vector `add` instructions).


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  https://reviews.llvm.org/D88214/new/

https://reviews.llvm.org/D88214