[llvm] d3a8e33 - [AMDGPU] Reformat SITargetLowering::isSDNodeSourceOfDivergence. NFC.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 28 06:51:02 PDT 2020
Author: Jay Foad
Date: 2020-09-28T14:42:05+01:00
New Revision: d3a8e333ec9db769b0335cd72ed6acf0d3d0b2ba
URL: https://github.com/llvm/llvm-project/commit/d3a8e333ec9db769b0335cd72ed6acf0d3d0b2ba
DIFF: https://github.com/llvm/llvm-project/commit/d3a8e333ec9db769b0335cd72ed6acf0d3d0b2ba.diff
LOG: [AMDGPU] Reformat SITargetLowering::isSDNodeSourceOfDivergence. NFC.
Added:
Modified:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index e3646d329118..b7b884544619 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -11675,46 +11675,40 @@ static bool isCopyFromRegOfInlineAsm(const SDNode *N) {
return false;
}
-bool SITargetLowering::isSDNodeSourceOfDivergence(const SDNode * N,
- FunctionLoweringInfo * FLI, LegacyDivergenceAnalysis * KDA) const
-{
+bool SITargetLowering::isSDNodeSourceOfDivergence(
+ const SDNode *N, FunctionLoweringInfo *FLI,
+ LegacyDivergenceAnalysis *KDA) const {
switch (N->getOpcode()) {
- case ISD::CopyFromReg:
- {
- const RegisterSDNode *R = cast<RegisterSDNode>(N->getOperand(1));
- const MachineRegisterInfo &MRI = FLI->MF->getRegInfo();
- const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
- Register Reg = R->getReg();
+ case ISD::CopyFromReg: {
+ const RegisterSDNode *R = cast<RegisterSDNode>(N->getOperand(1));
+ const MachineRegisterInfo &MRI = FLI->MF->getRegInfo();
+ const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
+ Register Reg = R->getReg();
- // FIXME: Why does this need to consider isLiveIn?
- if (Reg.isPhysical() || MRI.isLiveIn(Reg))
- return !TRI->isSGPRReg(MRI, Reg);
+ // FIXME: Why does this need to consider isLiveIn?
+ if (Reg.isPhysical() || MRI.isLiveIn(Reg))
+ return !TRI->isSGPRReg(MRI, Reg);
- if (const Value *V = FLI->getValueFromVirtualReg(R->getReg()))
- return KDA->isDivergent(V);
+ if (const Value *V = FLI->getValueFromVirtualReg(R->getReg()))
+ return KDA->isDivergent(V);
- assert(Reg == FLI->DemoteRegister || isCopyFromRegOfInlineAsm(N));
- return !TRI->isSGPRReg(MRI, Reg);
- }
- break;
- case ISD::LOAD: {
- const LoadSDNode *L = cast<LoadSDNode>(N);
- unsigned AS = L->getAddressSpace();
- // A flat load may access private memory.
- return AS == AMDGPUAS::PRIVATE_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS;
- } break;
- case ISD::CALLSEQ_END:
+ assert(Reg == FLI->DemoteRegister || isCopyFromRegOfInlineAsm(N));
+ return !TRI->isSGPRReg(MRI, Reg);
+ }
+ case ISD::LOAD: {
+ const LoadSDNode *L = cast<LoadSDNode>(N);
+ unsigned AS = L->getAddressSpace();
+ // A flat load may access private memory.
+ return AS == AMDGPUAS::PRIVATE_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS;
+ }
+ case ISD::CALLSEQ_END:
return true;
- break;
- case ISD::INTRINSIC_WO_CHAIN:
- {
-
- }
- return AMDGPU::isIntrinsicSourceOfDivergence(
- cast<ConstantSDNode>(N->getOperand(0))->getZExtValue());
- case ISD::INTRINSIC_W_CHAIN:
- return AMDGPU::isIntrinsicSourceOfDivergence(
- cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
+ case ISD::INTRINSIC_WO_CHAIN:
+ return AMDGPU::isIntrinsicSourceOfDivergence(
+ cast<ConstantSDNode>(N->getOperand(0))->getZExtValue());
+ case ISD::INTRINSIC_W_CHAIN:
+ return AMDGPU::isIntrinsicSourceOfDivergence(
+ cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
}
return false;
}
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