[PATCH] D88259: [SVE] Lower fixed length VECREDUCE_[SMAX|SMIN] to Scalable

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16004
   if (ResVT != ScalarOp.getValueType())
-    Res = DAG.getNode(ISD::TRUNCATE, DL, ScalarOp.getValueType(), Res);
+    Res = DAG.getAnyExtOrTrunc(Res, DL, ScalarOp.getValueType());
 
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paulwalker-arm wrote:
> I don't think an any extent is correct here as I'd expect SMINV to return a signed result and UMINV an unsigned one.
Please ignore my previous comment, I can see from the node's description is says `However, the reduction is performed using the vector element type and the value in the top bits is unspecified` so an any extent is exactly right.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88259/new/

https://reviews.llvm.org/D88259