[PATCH] D88259: [SVE] Lower fixed length VECREDUCE_[SMAX|SMIN] to Scalable

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally created this revision.
cameron.mcinally added reviewers: paulwalker-arm, efriedma, dancgr.
Herald added subscribers: llvm-commits, psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.
cameron.mcinally requested review of this revision.

This patch is pretty similar to the VECREDUCE_ADD patch, with some minor tweaks.

1. Results from the AArch64ISD::[SMAX|SMIN]V_PRED return element sized results. This requires an ANY_EXTEND for results < 32-bits, since Legalization promotes those results. (***Unless I misunderstood something***)

2. There is no NEON i64 vector support for SMAXV|SMINV, so use SVE for those.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D88259

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll

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